Autonomic computing utilizing a sequestered processing resource on a host CPU

A system comprising:

• a single central processing unit that includes a plurality of processor cores;
• a random access memory coupled to the plurality of processor cores;
• a physical input/output (I/O) device coupled to the plurality of processor cores;
• and
• platform firmware that selectively provides the plurality of processor cores access to the random access memory and the physical I/O device wherein the platform firmware
• sequesters one of the plurality of processor cores such that the sequestered processor core is not exposed to the remaining processor cores as a processor core,
• partitions a region of the random access memory to provide a service processing portion such that the sequestered processor core has access to all of the memory region and the remaining processor cores have access to at least a portion of the memory region but do not have access to the service processing portion, and
• hides the physical I/O device such that the sequestered processor core has access to the physical I/O device and the remaining processor cores do not have access to the physical I/O device.

A machine-readable medium comprising instructions stored therein which, when executed by a machine, cause the machine to perform operations including:

• sequestering one of a plurality of processor cores, the plurality of processor cores being part of a single central processing unit, such that the sequestered processor is not exposed to the remaining processor cores as a processor core;
• partitioning a memory region of a random access memory to provide a service processing portion such that the sequestered processor core has access to all of the memory region and the remaining processor cores have access to at least a portion of the memory region but do not have access to the service processing portion;
• and
• hiding a first input/output (I/O) device such that the sequestered processor core has access to the first I/O device and the remaining processor cores do not have access to the first I/O device.