Memory system and method for controlling the same, and method for maintaining data coherency
AssigneeInternational Business Machines Corporation
InventorNobuyuki Harada
Life of this patent
Estimating the term…
Abstract
A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporarily storing cache data and write data that the second device writes in the memory. The buffer of the memory controller temporarily stores cached data and the write data to be written on write access to the memory by the second device, which enables maintenance of data coherency while avoiding a write access retry by the second device.
Claims13
A memory system comprising:
- a bus;
- a memory, a memory controller, a first device having a cache, and a second device which are connected to the bus,
- wherein the memory controller includes a buffer for temporarily storing a cache data and a write data that the second device writes in the memory;
- and
- a retry control circuit for causing the write data to be temporarily stored in the buffer if a cache hit occurs in which the write data matches the cache data, the retry control circuit preventing the second device from performing a retry in response to an access retry request from the first device if the cache hit occurs.
In a memory system comprising a bus, and a memory, a memory controller, a first device having a cache, and a second device which are connected to the bus, a method for controlling the memory system when the second device makes write access to the memory, comprising the steps of:
- (a) comparing the address of a write data with the address of data in the cache;
- (b) if the address of the write data and the address of the cache data match each other, determining whether or not data stored at the matching address in the cache has been changed;
- (c) if the data has been changed, temporarily storing the write data in the buffer without allowing the second device to make a retry access;
- (d) temporarily storing the changed data contained in the cache into the buffer without overwriting the write data temporarily stored in the buffer;
- and
- (e) writing the changed data and the write data which are temporarily stored in the buffer into the memory as sequential data.
In a system in which a memory, a memory controller having a buffer, a plurality of bus masters, and a cache memory are interconnected through a bus, a method for maintaining data coherency by using a snooping algorithm, comprising the step of:
- if a write access by a bus master results in a snoop hit and the hit data in the cache memory has been updated, storing temporarily the write data of the bus master and the updated data in the cache memory into the buffer and then writing the write data and the updated data in the memory as sequential data, without executing an access retry by the bus master.
A distributed memory system, comprising:
- a first device having a cache memory;
- a first bus coupled to the first device;
- a second bus adapted to interface with a plurality of devices;
- a bus bridge interconnecting the first bus and the second bus;
- a system memory coupled to the second bus;
- a second device coupled to the second bus;
- a memory controller coupled to the second bus and including a buffer for temporarily storing a cache data and a write data the second device writes in the system memory;
- and
- a retry control circuit for causing the write data to be temporarily stored in the buffer if a cache hit occurs in which the write data matches the cache data, the retry control circuit preventing the second device from performing a retry in response to an access retry request from the first device if the cache hit occurs.
Dependencies are inferred from the claim text.