Instruction cache way prediction for jump targets

A method of enabling a cache prediction array from a plurality of cache prediction arrays comprising the steps of:

• providing an instruction at an address of a program counter for subsequent execution by a processor;
• determining whether the instruction is an instruction of a predetermined type;
• enabling one of a first cache prediction array if the instruction is other than an instruction of a predetermined type and a second cache prediction array if the instruction is an instruction of a predetermined type;
• enabling the first cache way prediction array and disabling the second cache way prediction array when the instruction indexed by the program counter is other than a branch instruction;
• and
• disabling the first cache way prediction array and enabling the second cache way prediction array when the instruction indexed by the program counter is a branch instruction.

A memory having stored therein data relating to instructions for performing the steps of:

• providing an instruction at an address of a program counter for subsequent execution by a processor;
• determining whether the instruction is an instruction of a predetermined type;
• enabling one of a first cache prediction array if the instruction is other than an instruction of a predetermined type and a second cache prediction array if the instruction is an instruction of a predetermined type;
• enabling the first cache way prediction array and disabling the second cache way prediction array when the instruction indexed by the program counter is other than a branch instruction;
• and
• disabling the first cache way prediction array and enabling the second cache way prediction array when the instruction indexed by the program counter is a branch instruction.

A cache memory for use in storage and retrieval of sequential and non-sequential instructions contained within a program stream, comprising:

• a first cache way prediction array for use in predicting a cache way for a first set of data;
• a second cache way prediction array for use in predicting a cache way for a second set of data;
• a decision circuit for receiving instruction data from the program stream and for selecting between the first cache way prediction array and the second cache way prediction array in dependence upon the instruction data;
• a program counter for use in execution of the instructions within the program stream;
• wherein the decision circuit comprises circuitry for:
• enabling the first cache way prediction array and disabling the second cache way prediction array when the instruction indexed by the program counter is other than a branch instruction;
• and
• disabling the first cache way prediction array and enabling the second cache way prediction array when the instruction indexed by the program counter is a branch instruction.

A storage medium having stored therein data, the data for use in implementing of integrated circuit designs, the data including data descriptive of circuit elements including:

• a tag array arranged in a plurality of rows and a plurality of cache ways having a plurality of storage locations located at each intersection of one of said plurality of rows and one of said plurality of cache ways, each of said storage locations from the plurality of storage locations for storing a tag address;
• a data array arranged in a plurality of rows and a plurality of cache ways having a plurality of storage locations located at each intersection of one of said plurality of rows and one of said plurality of cache ways, each of said storage locations from the plurality of storage locations for storing data bytes relating to instructions;
• a first cache way prediction array having a plurality of storage locations arranged in a plurality of rows, each storage location from the plurality for storing a first set of cache way prediction bits;
• a second cache way prediction array having a plurality of storage locations arranged in a plurality of rows, each storage location from the plurality for storing a second set of cache way prediction bits;
• and,
• a decision circuit for receiving an instruction from the program stream, the decision circuit for determining whether the instruction is one of a sequential and non sequential type and for enabling one of the first cache way prediction array and the second cache way prediction array, respectively, in dependence thereon, said enabled prediction array accessed at a request address to retrieve one of the first set of cache way prediction bits and the second set of cache way prediction bits, respectively, for enabling a cache way within the tag array and data array in dependence upon the retrieved prediction bits to facilitate retrieval of the tag address and the data bytes from the tag array and data array, respectively, within the enabled cache way;
• a program counter for use in execution of the instructions within the program stream and wherein the request address is derived from the program counter;
• and
• circuitry for enabling the first cache way prediction array and disabling the second cache way prediction array when the instruction indexed by the program counter is other than a branch instruction.