US 7,406,567 B1Granted

Algorithm to improve packet processing performance using existing caching schemes

AssigneeCisco Technology, Inc.

InventorsHarshad Nakil, Rajashekar Reddy, Hampapur Ajay, Nipa Kumar, Radesh Manian

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Abstract

A system and method for improving the speed of packet switching in a routing platform that maps shared I/O memory into two address spaces. The first address space is mapped with the cache attribute and uses the cache write through attribute. Addresses in this address space are not equal to the physical address in the shared I/O memory and are translated to the physical addresses. Code executed by the CPU to switch packets utilizes the first address space to access packet data. The second address space is mapped with the non-cache attribute and addresses in this space are equal to the physical addresses in the shared I/O memory. The second address space is utilized by I/O devices when accessing shared I/O memory. Addresses of buffers for storing packet data in the shared I/O memory are converted from the first address space to the second address space when given to I/O devices.

Claims7

Dependent claims

A method comprising:

mapping a shared memory into first and second virtual address spaces, with the shared memory holding buffer data structures and non-buffer data structures, with the buffer data structures and non-buffer data structures shared between Input/Output (I/O) devices which send and receive packets and a Central Processing Unit (CPU);
setting a cache attribute for the first virtual address space and utilizing the cache write through algorithm when writing cached data with addresses in the first virtual address space, where the first virtual address space is utilized only by the CPU and the CPU utilizes addresses in the first virtual address space to access only buffer data structures;
reporting addresses in the first virtual address space to code executed by the CPU which implements switching;
returning pointers to buffer data structures, which store packet data, where pointers returned point to addresses in the first virtual address space when allocating memory;
setting a non-cache attribute for the second virtual address space, where non-buffer data structures held in the shared memory are accessed utilizing addresses in the second address space;
converting a returned pointer to a buffer data structure from a pointer to an address in the first virtual address space to a converted pointer to a corresponding address in the second virtual address space prior to passing the pointer from the CPU to an I/O device;
at the I/O device, using the converted pointer to access packet data stored in a buffer data structure in the shared memory;
and
at the CPU, invalidating the cache lines corresponding to the addresses of a received packet before accessing data in the received packet.

6 more elements

One or more computer readable storage media encoded with software comprising computer executable instructions and when the software is executed operable to:

map a shared to memory into first and second virtual address spaces, with the shared memory including buffer data structures and non-buffer data structures, with the buffer data structures and non-buffer data structures shared between Input/Output (I/O) devices which send and receive packets and a Central Processing Unit (CPU);
set a cache attribute for the first virtual address space and utilize the cache write through algorithm when writing cached data with addresses in the first virtual address space, where the first virtual address space and utilize the cache write through algorithm when writing cached data with addresses int he first virtual address space, where the first virtual address space is utilized only by the CPU and the CPU utilizes addresses int he first virtual address space to access only buffer data structures;
report addresses in the first virtual address space to code executed by the CPU which implements switching;
return pointers to buffer data structures, which store packet data, where pointers returned point to addresses in the first virtual address space when allocating memory;
set a non-cache attribute for the second virtual address space, where non-buffer data structures held in the shared memory are accessed utilizing addresses in the second virtual address space;
convert a returned pointer to a buffer data structure from a pointer to an address in the first virtual address space to a converted pointer to a corresponding address in the second virtual address space prior to passing the pointer from the CPU to an I/O device;
cause said I/O device to use the converted pointer to access packet data stored in a buffer data structure in the shared memory;
and
cause the CPU to invalidate cache lines corresponding to the addresses of a received packet before accessing data in the received packet.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/291,894Filed 8 Nov 2002
Granted: 29 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/084
Multiuser, multiprocessor or multiprocessing cache systems: with a shared cache
G06F 12/0835
Using a bus scheme, e.g. with bus monitoring or watching means: for main memory peripheral accesses
G06F 12/1036
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: for multiple virtual address spaces,…
G06F 12/109
Address translation: for multiple virtual address spaces, e.g. segmentation