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US 7,406,566 B2Granted
Ring interconnect with multiple coherence networks
AssigneeIntel Corporation
InventorBenjamin Tsien
Life of this patent
Estimating the term…
Abstract
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.
Claims26
An apparatus comprising:
- a first cache agent;
- a second cache agent coupled to the first cache agent;
- a concentric ring interconnect coupled to the first and second cache agents including a first and second signal;
- a first protocol agent to receive a first cache operation information from the first cache agent in the first signal and a second cache operation information from the second cache a gent in the second signal during the same clock cycle, wherein the first cache operation information includes snoop data, write-back information, and data request commands and the second cache operation information includes fill acknowledge information and non-data snoop response information.
1 more element
A system comprising:
- a microprocessor comprising a first network having only two signals in which to transmit a first cache operation information between a first set of cache agents and a first protocol agent and between a second set of cache agents and a second protocol agent respectively, the microprocessor further including a second network having only two signals in which to transmit a second cache operation information between the first set of cache agents and the first protocol agent and between the second set of cache agents and the second protocol agent, respectively, within the same clock cycle as the first cache operation information, wherein the first cache operation information includes snoop data, write-back information, and data request commands and the second cache operation information includes fill acknowledge information and non-data snoop response information;
- a memory coupled to the microprocessor.
An processor comprising:
- a ring network of cache agents, a first set of the cache agents to communicate via a first protocol agent and a second set of cache agents to communicate via a second protocol agent, the first and second protocol agents comprising a first and second first-in-first-out (FIFO) buffer to store a first information during a first clock cycle and a second information during a second clock cycle;
- a plurality of routing agents to route the first information between the first set of cache agents and the first protocol agent using only two signal lines and the second information between the second set of cache agents and the second protocol agent using only two signal lines, respectively, wherein the first information includes snoop data, write-back information, and data request commands and the second information includes fill acknowledge information and non-data snoop response information.
A method comprising:
- transmitting a first cache operation through a communication channel, having only two signals, in a first direction;
- transmitting a second cache operation through a communication channel, having only two signals, in a second direction during the same clock cycle as transmitting the first cache operation on the first direction, wherein the first cache operation includes snoop data, write-back information, and data request commands and the second cache operation includes fill acknowledge information and non-data snoop response information.
Dependencies are inferred from the claim text.