Distributed FIFO
AssigneeAltera Corporation
InventorPeter Bain
Life of this patent
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Abstract
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.
Claims20
A method of writing to a FIFO comprising a plurality of sub-blocks, the method comprising:
- providing a write command to a first FIFO sub-block, the first FIFO sub-block comprising a first plurality of storage locations;
- providing data to the first FIFO sub-block;
- determining whether each of the first plurality of storage locations in the first FIFO sub-block have been written to, and if not, writing the data to one of the first plurality of storage locations in the first FIFO sub-block, else;
- providing the write command to a second FIFO sub-block, the second FIFO sub-block comprising a second plurality of storage locations;
- and
- determining whether each of the second plurality of storage locations in the second FIFO sub-block have been written to, and if not, writing the data to one of the second plurality of storage locations in the second FIFO sub-block.
A method of reading data from a FIFO comprising a plurality of sub-blocks, the method comprising:
- providing a read command to a first FIFO sub-block, the first FIFO sub-block comprising a first plurality of storage locations;
- determining whether data has been read from each of a second plurality of storage locations in a second FIFO sub-block, and if it has, then reading data from one of the first plurality of storage locations in the first FIFO sub-block, else,
- providing the read command to the second FIFO sub-block;
- and
- determining whether data has been read from each of a third plurality of storage locations in a third FIFO sub-block, and if it has, then reading data from one of the second plurality of storage locations in the second FIFO sub-block.
An integrated circuit comprising a FIFO, the FIFO comprising:
- a first FIFO sub-block comprising:
- a first read address counter configured to provide a first read address;
- a first write address counter configured to provide a first write address;
- a first memory array;
- and
- write circuitry to receive a write signal and write data, to write the write data to the first memory array when the first write address counter is not at a first count, and to pass the write signal and write data to a second FIFO sub-block when the first write address counter is at the first count;
- and
- the second FIFO sub-block comprising:
- a second read address counter configured to provide a second read address;
- a second write address counter configured to provide a second write address;
- a second memory array;
- and
- write circuitry to receive the write signal and write data from the first FIFO sub-block.
Dependencies are inferred from the claim text.