Bus configuration circuit
AssigneeOki Electric Industry Co., Ltd.
InventorYuzo Ishihara
Life of this patent
Estimating the term…
Abstract
A bus configuration circuit includes a first group having a first master module, a first slave module and a first bus module group; a second master module and a second slave module disposed outside the first group and connected thereto by a second bus module group; and a third slave module disposed outside the first group. A first control signal is output from the first bus module group indicative of whether an access destination of the first master module is the first slave module. A second control signal is output from the first slave module indicative of the accessed status of the first slave module. The third slave module consequently outputs a third control signal responsive to the first and second control signals.
Claims9
A bus configuration circuit, comprising:
- a first group that consists of a first master module, a first slave module controlled by the first master module, a first bus module group that connects the first master module and the first slave module, and a decoder connected to the first bus module group, the first group disposed within a first platform;
- a second master module and a second slave module disposed outside the first platform and connected to the first group via the first bus module group by a second bus module group, the second bus module group disposed outside the first platform,
- a first control signal output from the decoder within the first bus module group, the first control signal indicative of whether an access destination of the first master module corresponds to the first slave module;
- a second control signal output from the first slave module through the first bus module group and indicative of accessed status of the first slave module;
- and
- a third slave module disposed outside the first platform and that receives the first and second control signals,
- the third slave module including a selector that selectively outputs one of the second control signal and an internally generated signal as a third control signal to the first master module, the second master module, the first slave module and the second slave module via the second bus module group and the first bus module group, responsive to the first control signal and the second control signal.
A bus configuration circuit, comprising:
- a first group that consists of a first master module, a first slave module controlled by the first master module, and a first bus module group that connects the first master module and the first slave module, the first group disposed within a first platform;
- a second master module and a second slave module disposed outside the first platform and connected to the first group via the first bus module group by a second bus module group, the second bus module group disposed outside the first platform;
- a first control signal output from the first bus module group according to whether an access destination of the first master module corresponds to the first slave module;
- a second control signal output from the first slave module through the first bus module group and indicative of accessed status of the first slave module;
- and
- a third slave module disposed outside the first platform and coupled to receive the first and second control signals, that outputs a third control signal to the second master module and the second slave module directly via the second bus module group, and that outputs the third control signal to the first master module and the first slave module via the second bus module group followed by the first bus module group, responsive to the first control signal and the second control signal.
Dependencies are inferred from the claim text.