Deterministic microcontroller with configurable input/output interface

A microcontroller comprising:

• a central processor unit;
• a context manager comprising hardware circuitry operable to selectively determine one of a plurality of contexts of operation of said microcontroller;
• a plurality of sets of hardware registers, each set of registers being usable to store context information for a predetermined corresponding one of said plurality of contexts, said context manager operating to select a set of hardware registers from said plurality of sets of hardware registers corresponding to the determined one context of said plurality of context, said central processor unit utilizing said selected set of hardware registers;
• a user programmable cache coupled to said central processor unit;
• and
• a plurality of programmable input/output controllers coupled to said central processor unit, each of said programmable input/output controllers being programmable to interface to one or more of a plurality of standard peripheral interfaces, each of said programmable input/output controllers being coupled to said central processor unit to transfer data between said central processor unit and corresponding one or more peripheral units, each said programmable input/output controller being selectively programmed and operable to in accordance with a corresponding selected predetermined interface for use by said peripheral unit, each said programmable input/output controller comprising:
• a program memory, said program memory being programmably arranged into a plurality of program thread sections, said memory being allocated for said program thread sections based upon the number or said program thread sections, each of said program thread sections being programmably selectable in size;
• the number of said plurality of sections and the size of said sections beta programmed in accordance with at least one selected predetermined interface for said peripheral unit;
• a micro sequencer operable in accordance with each of said program thread sections to provide program control of said configurable controller;
• a configuration manager coupled to said micro sequencer and coupled to said memory to load predetermined programs received via said internal bus interface into each said section input portion and each said section output portion;
• a bus interface unit;
• a plurality of registers coupled to said bus interface unit;
• and
• a multiplexer circuit coupled to a plurality of input/output terminals and to said plurality of registers;
• said multiplexer circuit being programmably operable to selectively couple each terminal of said plurality of input/output terminals to said plurality of registers based upon said at least one selected predetermined protocol.

A microcontroller comprising:

• a central processor unit, said central processor unit comprising a plurality of sets of hardware registers, each set of registers being usable to store context information for a predetermined corresponding one of said plurality of contexts, a plurality of sets of hardware registers, each set of registers being usable to store context information for a predetermined corresponding one of said plurality of contexts;
• a context manager comprising hardware circuitry operable to selectively determine one of a plurality of contexts of operation of said microcontroller, said context manager operating to select a set of hardware registers from said plurality of sets of hardware registers corresponding to the determined one context of said plurality of context, said central processor unit operatively utilizing said selected set of hardware registers;
• a first bus;
• a plurality of programmable input/output controllers coupled to said central processor unit to transfer data between said central processor unit and a corresponding plurality of peripheral units;
• each said programmable input/output controller being selectively programmed and operable to in accordance with a corresponding selected corresponding one predetermined interface of a plurality of predetermined interfaces for use by a corresponding one peripheral unit;
• each said programmable input/output controller comprising:
• a first bus interface unit coupleable to said first bus for transferring data between said programmable input/output controller and said first bus;
• a program memory, said program memory being programmably arranged into a plurality of program thread sections, said memory being allocated for said program thread sections based upon the number or said program thread sections, each of said program thread sections being programmably selectable in size;
• the number of said plurality of sections and the size of said sections being programmed in accordance with at least one selected predetermined interface for said peripheral unit;
• a configuration manager coupleable to said first bus and coupled to said memory to load predetermined programs received via said first bus;
• a plurality of terminals;
• and
• a multiplexer circuit coupled to said plurality of terminals and to said plurality of registers;
• said multiplexer circuit being programmably operable to selectively couple each terminal of said plurality of to said input/output controller based upon said selected predetermined interface.