Adder structure with midcycle latch for power reduction

A method comprising:

• the steps of:
• providing a complete multiple stage digital adder circuit having at least three stages for generating and propagating groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic CMOS logic in a carry network,
• implementing logic functions and processing input variables from a one stage and outputting result values to a succeeding stage of said added circuit, and, while
• a) operating at least one logic stage of relatively high switching activity implemented in static CMOS hardware logic and at least one logic stage of relatively low switching activity implemented in dynamic CMOS hardware logic,
• b) operating a predetermined stage with an input (60, 62) directly obtained from a stage being positioned earlier than a preceding bypass stage preceding said predetermined stage, in order to avoid input from said earlier stage into said bypass stage.