Method of generating a cycle-efficient bit-reverse index array for a wireless communication system
AssigneeTexas Instruments Incorporated
InventorDavid P. Magee
Life of this patent
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Abstract
An efficient method of generating a bit-reverse index array in real time without performing any bit manipulation for a wireless communication system.
Claims14
A programmable processing device for generating a bit-reverse index array of memory locations in a memory processed by a central processing unit for a wireless communication system, the programmable processing device executing instructions embodied in a portion of said memory instructing the programmable processing device to perform the steps of:
- (a) initializing a first memory location of an index array of memory locations, in the memory, to 0;
- using the central processing unit:
- (b) multiplying the initialized first memory location by the number 2 to generate a first portion of the index array of memory locations;
- (c) adding the number 1 to the first portion of the index array to generate a second portion of the index array of memory locations, wherein the first portion and the second portion comprise a new set of numbers;
- (d) multiplying each number in the new set of numbers by the number 2 to generate a new first portion of the index array of memory locations, wherein the new first portion of the index array comprises a new set of numbers;
- (e) adding the number 1 to each number in the new first portion of the index array to generate a new second portion of the index array, wherein the new first portion and the new second portion comprises a new set of numbers;
- and
- (f) repeating steps (d) and (e) until the index array of memory locations grows to a bit-reverse index array of memory locations having a desired length.
A programmable processing device coupled to a memory for generating a bit-reverse index array of memory locations, the programmable processing device executing instructions embodied in a portion of said memory instructing the programmable processing device to perform the steps of:
- (a) initializing a first value of an index array stored in the memory to 0 to generate a first set of the index array of memory locations;
- using a central processing unit:
- (b) adding the number 1 to the first set of memory locations to generate a second set of memory locations, wherein the first set and the second set comprise a new set of numbers;
- (c) multiplying each number in the new set of numbers by the number 2 to generate a new first set of memory locations, wherein the new first set of the index array comprises a new set of numbers;
- (d) adding the number 1 to each number in the new first set of the index array to generate a new second set of memory locations, wherein the new first set and the new second set comprises a new set of numbers;
- and
- (e) repeating steps (c) and (d) until the index array of memory locations grows to a bit-reverse index array of memory locations having a desired length.
A programmable processing device coupled to a memory for generating a bit-reversed index array of memory locations of n-bit binary values, the programmable processing device executing instructions embodied in a portion of said memory instructing the programmable processing device to perform the steps of:
- (a) initializing a first set of memory locations stored in the memory;
- using a central processing unit:
- (b) computing each value in the first set of memory locations by multiplying each said value by a first predetermined amount;
- (c) updating each value in the first set of memory locations;
- (d) computing each value in a second set of memory locations by adding a second predetermined amount to a corresponding one of the first set of memory locations;
- (e) updating each value in the second set of memory locations;
- (f) re-defining the first set of memory locations to include the second set of memory locations;
- and
- (g) repeating steps (b) through (f) until the re-defined first set of memory locations is of a desired length, wherein the index to each memory location in a set of memory locations being the bit reverse of the value stored in that element of the set of memory locations.
Dependencies are inferred from the claim text.