Back to results
US 7,406,365 B2Granted
Power manager with selective load reduction
AssigneeIntel Corporation
InventorsAnnabelle Pratt, Eugene Gorbatov, Pavan Kumar, Tomm V. Aldridge
Life of this patent
Estimating the term…
Abstract
In some embodiments, a power manager may be coupled to a load circuit and configured to receive an input signal indicating a line disturbance on a power supply line and to reduce a load requirement of the load circuit in accordance with the received signal. The power manager may be configured to selectively reduce power to components with low entrance latency while continuing to provide full power to components with high entrance latency. Other embodiments are disclosed and claimed.
Claims28
An apparatus, comprising:
- a load circuit;
- and
- a power manager coupled to the load circuit and configured to receive an input signal indicating a line disturbance on a power supply line and to reduce a load requirement of the load circuit in accordance with the received signal,
- wherein the power manager is configured to selectively reduce power to components with low entrance latency while continuing to provide full power to components with high entrance latency.
1 more element
A method, comprising:
- receiving a signal indicating a line disturbance on a power supply line;
- and
- selectively reducing power to components with low entrance latency in response to the signal while continuing to provide full power to components with high entrance latency.
A system, comprising:
- a power supply unit;
- a load circuit connected to the power supply unit;
- and
- a power manager coupled between the power supply unit and the load circuit, wherein the power manager is configured to reduce a load requirement of the load circuit in response to a power disturbance signal received from the power supply unit,
- and wherein the power manager is configured to selectively reduce power to components with low entrance latency in accordance with the power disturbance signal while continuing to provide full power to components with high entrance latency.
2 more elements
Dependencies are inferred from the claim text.