Clock generation circuit and semiconductor device provided therewith
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorTakeshi Osada
Life of this patent
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Abstract
It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.
Claims12
A semiconductor device comprising:
- an antenna;
- a demodulation circuit operationally connected to the antenna;
- a clock generation circuit operationally connected to the demodulation circuit;
- and
- a modulation circuit operationally connected to the antenna,
- wherein the clock generation circuit comprises a PLL circuit, an oscillator circuit and a determination circuit,
- wherein, in a signal input portion, the determination circuit is a circuit which determines a first period from receiving a reception start signal to receiving a reception end signal and a second period except for the period from receiving a reception start signal to receiving a reception end signal, and
- wherein a switch for selecting a connection of the PLL circuit to a signal output portion in the first period and selecting a connection of the oscillator circuit to the signal output portion in the second period is provided.
A semiconductor device comprising:
- a resonant circuit;
- a demodulation circuit operationally connected to the resonant circuit;
- a clock generation circuit operationally connected to the demodulation circuit;
- and
- a modulation circuit operationally connected to the resonant circuit,
- wherein the clock generation circuit comprises a PLL circuit, an oscillator circuit and a determination circuit,
- wherein, in a signal input portion, the determination circuit is a circuit which determines a first period from receiving a reception start signal to receiving a reception end signal and a second period except for the period from receiving a reception start signal to receiving a reception end signal, and
- wherein a switch for selecting a connection of the PLL circuit to a signal output portion in the first period and selecting a connection of the oscillator circuit to the signal output portion in the second period is provided.
A semiconductor device comprising:
- an antenna;
- a demodulation circuit operationally connected to the antenna;
- a clock generation circuit operationally connected to the demodulation circuit;
- and
- a modulation circuit operationally connected to the antenna,
- wherein the clock generation circuit comprises a PLL circuit, an oscillator circuit and a determination circuit,
- wherein, in a signal input portion, the determination circuit is a circuit which determines a first period from receiving a reception start signal to receiving a reception end signal and a second period except for the period from receiving a reception start signal to receiving a reception end signal,
- wherein a switch for selecting a connection of the PLL circuit to a signal output portion in the first period and selecting a connection of the oscillator circuit to the signal output portion in the second period is provided, and
- wherein each of the PLL circuit, the oscillator circuit and the determination circuit comprises a transistor.
Dependencies are inferred from the claim text.