Back to results
US 7,406,147 B2Granted
Shift register
AssigneeWintek Corporation
InventorsShin-Tai Lo, Ching-Fu Hsu, Wen-Tui Liao
Life of this patent
Estimating the term…
Abstract
A shift register includes multiple stages connected with each other in succession. The shift register stores the threshold voltage of an amorphous silicon thin-film transistor in a capacitor. During operation, the bias applied to the transistor is adjusted according to the threshold voltage stored in the capacitor.
Claims24
A shift register, comprising:
- N number (N is a positive integer) of unit stages each having an input terminal, wherein a first unit stage receives a threshold signal as a drive signal via the input terminal for generating a first output signal, a Qth (Q is a positive integer;
- 1<Q≦N) unit stage receives a (Q−1)th output signal for generating a Qth output signal, each odd-numbered unit stage receives an odd-numbered clock signal, a first odd-numbered control signal, a second odd-numbered control signal and a third odd-numbered control signal as drive signals, each even-numbered unit stage receives an even-numbered clock signal, a first even-numbered control signal, a second even-numbered control signal and a third even-numbered control signal as drive signals, and wherein each unit stage comprises:
- a pull-up unit comprising a first node for receiving the odd-numbered clock signal or the even-numbered clock signal;
- a pull-up drive unit connected to the first node for driving the pull-up unit according to the threshold signal or the output signal of a preceding unit stage so as to supply the odd-numbered clock signal or the even-numbered clock signal to an output terminal to generate the output signal;
- a first pull-down unit comprising a first transistor, the drain of the first transistor being connected to the output terminal, its source being connected to a first power voltage source having a first power voltage, and its gate being connected to a second node;
- a second pull-down unit comprising a second transistor, the drain of the second transistor being connected to the first node, its gate being connected to second node, and its source being connected to the first power voltage source;
- and
- a pull-down memory control unit comprising a capacitor whose two ends are respectively connected to the second node and a third node, the pull-down memory control unit receiving a first odd-numbered control signal or a first even-numbered control signal to increase the voltage of the second node to a second power voltage so as to turn on the first and the second transistors and to decrease the voltage of the third node to the first power voltage, and receiving a second odd-numbered control signal or a second even-numbered control signal to keep the voltage in third node at the first power voltage, with the capacitor maintaining a voltage difference between the second node and the third node;
- wherein the first transistor supplies the first power voltage to the output terminal when the first transistor is in the on-state, the second transistor supplies the first power voltage to the first node when the second transistor is in the on-state, and the pull-up drive unit turns off the pull-up unit according to the first power voltage of the first node.
6 more elements
A unit stage of a shift register for receiving a clock signal, a first control signal, a second control signal, a third control signal, a feedback control signal, and an input signal as drive signals to generate an output signal, the unit stage comprising:
- a pull-up unit comprising a first node for receiving the clock signal;
- a pull-up drive unit connected to the first node for driving the pull-up unit according to the input signal so as to supply the clock signal to an output terminal to generate the output signal;
- a first pull-down unit comprising a first transistor, the drain of the first transistor being connected to the output terminal, its source being connected to a first power voltage source having a first power voltage, and its gate being connected to a second node;
- a second pull-down unit, comprising:
- a second transistor, the drain of the second transistor being connected to the first node, its gate being connected to the second node, and its source being connected to the first power voltage source;
- and
- a third transistor, the drain of the third transistor being connected to the first node, its gate receiving the feedback control signal, and its source being connected to the first power voltage source;
- and
- a pull-down memory control unit comprising a capacitor whose two ends are respectively connected to the second node and the third node, the pull-down memory control unit receiving the first control signal to increase the voltage of the second node to a second power voltage so as to turn on the first and the second transistors and to decrease the voltage of the third node to the first power voltage, and receiving the second control signal to keep the voltage of the third node at the first power voltage, with the capacitor maintaining a voltage difference between the second node and the third node;
- wherein the first transistor supplies the first power voltage to the output terminal when the first transistor is in the on-state, the second transistor supplies the first power voltage to the first node when the second transistor is in the on-state, the third transistor supplies the first power voltage to the first node when the third transistor is turned on by the feedback control signal, and the pull-up drive unit turns off the pull-up unit according to the first power voltage of the first node.
7 more elements
A unit stage of a shift register, comprising:
- a pull-up unit comprising a first node for receiving a clock signal;
- a pull-up drive unit connected to the first node for driving the pull-up unit according to an input signal so as to supply the clock signal to an output terminal to generate an output signal;
- a first pull-down unit comprising a first transistor, the drain of the first transistor being connected to the output terminal, its source being connected to a first power voltage source having a first power voltage, and its gate being connected to a second node;
- a second pull-down unit comprising a second transistor, the drain of the second transistor being connected to the first node, its gate being connected to the second node, and its source being connected to the first power voltage source;
- and
- a pull-down memory control unit comprising a capacitor whose two ends are respectively connected to the second node and a third node, the pull-down memory control unit receiving a first control signal to increase the voltage of the second node to a second power voltage of a second power voltage source so as to turn on the first and the second transistors and to decrease the voltage of the third node to the first power voltage, and receiving a second control signal to keep the voltage of the third node at the first power voltage, with the capacitor maintaining a voltage difference between the threshold voltage of the first transistor and the threshold voltage of the second transistor;
- wherein the first transistor supplies the first power voltage to the output terminal when the first transistor is in the on-state, the second transistor supplies the first power voltage to the first node when the second transistor is in the on-state, and the pull-up drive unit turns off the pull-up unit according to the first power voltage of the first node.
4 more elements
Dependencies are inferred from the claim text.