Shift register circuit

A shift register circuit controlled by a first signal, a second signal, a third signal, and a fourth signal, the shift register circuit comprising:

• a first transistor having a gate for receiving the second signal and a first source/drain for receiving the third signal;
• a second transistor having a gate coupled to a second source/drain of the first transistor and a first source/drain for receiving the first signal;
• a third transistor having a first source/drain coupled to a second source/drain of the second transistor and a second source/drain for receiving a low level voltage;
• a fourth transistor having a first source/drain coupled to a second source/drain of the second transistor, a second source/drain for receiving the low level voltage and a gate coupled to the fourth signal;
• a first inverter having an input terminal for receiving the third signal;
• a second inverter having an input terminal coupled to a first source/drain of the fourth transistor, and an output terminal coupled to a gate of the third transistor;
• a fifth transistor having a first source/drain coupled to an output terminal of the first inverter, and a gate coupled to a second source/drain of the first transistor;
• a sixth transistor having a first source/drain coupled to a second source/drain of the fifth transistor, a second source/drain for receiving the low level voltage, and a gate coupled to the output terminal of the second inverter;
• a seventh transistor having a first source/drain for receiving a high level voltage, and a gate coupled to the second source/drain of the fifth transistor;
• and
• an eighth transistor having a first source/drain coupled to a second source/drain of the seventh transistor, a second source/drain for receiving the low level voltage, and a gate coupled to the output terminal of the the second inverter.