Jitter detection circuit
AssigneeNEC Electronics Corporation
InventorTadayoshi Mori
Life of this patent
Estimating the term…
Abstract
There is provided a jitter detection circuit of a phase locked loop circuit, comprising a comparison circuit. The comparison circuit compares an input clock that is inputted to the phase locked loop circuit and an output clock that is outputted by the phase locked loop circuit. When it is determined that the frequency difference between the input clock and the output clock is outside a predetermined range, the comparison circuit outputs a first anomaly signal. The comparison circuit is constituted as a digital circuit.
Claims8
The jitter detection circuit of a phase locked loop circuit, comprising:
- a comparison circuit that compares an input clock that is inputted to the phase locked loop circuit and an output clock that is outputted by the phase locked loop circuit and which, when the frequency difference between the input clock and the output clock is outside a predetermined range, outputs a first anomaly signal,
- wherein the comparison circuit is constituted as a digital circuit, and
- wherein the comparison circuit counts the number of pulses of the output clock in a reference time corresponding to m-multiplied cycle (m is a natural number) of the input clock and determines whether the frequency difference is outside the predetermined range on the basis of the count value.
The jitter detection circuit of a phase locked loop circuit comprising:
- a comparison circuit that compares an input clock that is inputted to the phase locked loop circuit and an output clock that is outputted by the phase locked loop circuit and which, when the frequency difference between the input clock and the output clock is outside a predetermined range, outputs a first anomaly signal,
- wherein the comparison circuit is constituted as a digital circuit;
- and
- a switching circuit which receives a plurality of clocks including the output clock and outputs any one clock among the plurality of clocks,
- wherein the switching circuit selects and, outputs a clock excluding the output clock when the first anomaly signal is outputted by the comparison circuit.
Dependencies are inferred from the claim text.