Transceiver having a jitter control processor with a receiver stage and a method of operation thereof
AssigneeAgere Systems Inc.
InventorRoy B. Blake
Life of this patent
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Abstract
The present invention provides a transceiver couplable to a communications network having a jitter control processor and method of operating the same. In one aspect of the present invention, the jitter control processor of the transceiver includes a receiver stage. The receiver stage includes: (1) a receive time error measurement system configured to generate a receive time error signal as a function of a receive clock signal experiencing jitter and a feedback signal, (2) a jitter processing circuit configured to develop a dejittered control signal as a function of the time error signal, and (3) a clock generator system configured to provide the feedback signal as a function of the dejittered control signal and a transceiver local clock signal.
Claims20
A transceiver couplable to a communications network having a jitter control processor with a receiver stage, said receiver stage, comprising:
- a receive time error measurement system configured to generate a receive time error signal as a function of a receive clock signal experiencing jitter and a feedback signal;
- a jitter processing circuit configured to develop a dejittered control signal as a function of said time error signal;
- and
- a clock generator system configured to provide said feedback signal as a function of said dejittered control signal and a transceiver local clock signal, said feedback signal providing a filtered frame reference for adjusting said receive clock signal with respect to said transceiver local clock signal.
A method of operating a transceiver couplable to a communications network having a jitter control processor with a receiver stage, comprising:
- generating a receive time error signal as a function of a receive clock signal experiencing jitter and a feedback signal;
- developing a dejittered control signal as a function of said time error signal;
- and creating said feedback signal as a function of said dejittered control signal and a transceiver local clock signal, said feedback signal providing a filtered frame reference for adjusting said receive clock signal with respect to said transceiver local clock signal.
Dependencies are inferred from the claim text.