Programmable logic device including programmable multi-gigabit transceivers

A programmable logic device comprises:

• clock management module operably coupled to provide a reference clock from one of a plurality of clock sources;
• transmit physical media attachment (PMA) module operably coupled to convert parallel transmit data into serial transmit data, wherein the transmit PMA module receives the parallel transmit data in accordance with a parallel transmit clock and transmits the serial transmit data in accordance with a serial transmit clock, wherein the transmit PMA module generates the parallel transmit clock, the serial transmit clock, and a transmit programmable logic clock based on the reference clock;
• receive PMA module operably coupled to convert serial receive data into parallel receive data, wherein the receive PMA module receives the serial receive data in accordance with a serial receive clock and provides the parallel receive data in accordance with a parallel receive clock, wherein the receive PMA module generates the serial receive clock, the parallel receive clock, and a receive programmable logic clock based on the reference clock;
• transmit physical coding sublayer (PCS) module operably coupled to convert transmit data words into the parallel transmit data in accordance with the parallel transmit clock;
• receive PCS module operably coupled to convert the parallel receive data into receive data words in accordance with the parallel receive clock;
• programmable logic fabric operably coupled to produce the transmit data words in accordance with the transmit programmable logic clock and to process the received data words in accordance with the receive programmable logic clock;
• wherein the plurality of clock source further comprises a low jitter external clock source, a recovered clock, and internal clock of the programmable logic fabric;
• and
• wherein the receive PCS module further comprises:
• programmable data alignment module operably coupled to align data words of the parallel receive data in accordance with a receive interface setting and the parallel transmit clock to produce aligned data words wherein size and rate of the aligned data words are set based on the receive interface setting;
• programmable descramble and decode module operably coupled to descramble, decode, or pass the aligned data words in accordance with the receive interface setting to produce processed aligned data words, wherein the receive interface setting indicates descrambling, decoding, or passing of the aligned data words, wherein the receive interface setting further indicates a type of descrambling when the programmable descramble and decode module is descrambling the aligned data words and further indicates a type of decoding when the programmable descramble and decode module is decoding the aligned data words;
• programmable storage module operably coupled to elastic store or pass the processed data words in accordance with the receive interface setting to produce stored data words;
• and
• programmable decode and verify module operably coupled to decode, verify or pass the stored data words in accordance with the receive interface setting and a programmed logic interface setting to produce the receive data words, wherein the receive interface setting indicates the decoding, the verifying or the passing of the stored data words, indicates a second type of decoding when the programmable decode and verify module is decoding the stored data words and indicates a type of verifying when the programmable decode and verify module is verifying the stored data words and wherein the programmed logic interface setting indicates rate and size of the received data words.

A programmable multi-gigabit transceiver comprises:

• a transmit section operably coupled to convert transmit data words into transmit serial data in accordance with a transmit setting;
• a receive section operably coupled to convert receive serial data stream into receive data words in accordance with a receive setting;
• an interface to programmable logic section operably coupled to provide the transmit data words from the programmable logic section to the transmit section in accordance with the transmit setting and to receive the receive data words from the receive section in accordance with the receive setting;
• and
• control module operably coupled to produce the transmit setting and the receive setting based on transceiver operational requirements;
• wherein the control module further functions to:
• generate the receive setting to enable, logically disable, or physically disable at least one element of a programmable PMA receiver module of the receiver section;
• generate the transmit setting to enable, logically disable, or physically disable at least one element of a programmable PMA transmit module of the transmit section;
• generate the transmit setting to enable, logically disable, or physically disable at least one element of a programmable PCS transmit module of the transmit section;
• and
• generate the receive setting to enable, logically disable, or physically disable at least one element of a programmable PCS receive module of the receive section;
• wherein the receive section further comprises:
• a programmable physical media attachment (PMA) receive module operably coupled to convert the receive serial data into receive parallel data in accordance with the receive setting;
• and
• a programmable physical coding sublayer (PCS) receive module operably coupled to convert the receive parallel data into the receive data words in accordance with the receive setting;
• and
• wherein the programmable PCS receive module further comprises:
• programmable data alignment module operably coupled to align the receive parallel data in accordance with the receive setting to produce aligned data words, wherein size and rate of the aligned data words are set based on the receive setting;
• programmable descramble and decode module operably coupled to descramble, decode, or pass the aligned data words in accordance with the receive setting to produce processed aligned data words, wherein the receive setting indicates descrambling, decoding, or passing of the aligned data words, wherein the receive setting further indicates a type of descrambling when the programmable descramble and decode module is descrambling the aligned data words and further indicates a type of decoding when the programmable descramble and decode module is decoding the aligned data words;
• programmable storage module operably coupled to elastic store or pass the processed data words in accordance with the receive setting to produce stored data words;
• and
• programmable decode and verify module operably coupled to decode, verify or pass the stored data words in accordance with the receive setting and the programmed logic interface setting to produce the receive data words, wherein the receive setting indicates the decoding, the verifying or the passing of the stored data words, indicates a second type of decoding when the programmable decode and verify module is decoding the stored data words and indicates a type of verifying when the programmable decode and verify module is verifying the stored data words and wherein the programmed logic interface setting indicates rate and size of the received data words.

A programmable logic device comprises:

• a plurality of programmable multi-gigabit transceivers, wherein each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings to transceive data;
• programmable logic fabric operably coupled to the plurality of programmable multi-gigabit transceivers, wherein the programmable logic fabric is configured to process at least a portion of the data;
• control module operably coupled to produce the plurality of transceiver settings based on a desired mode of operation of the programmable logic device;
• wherein each of the plurality of programmable multi-giga bit transceivers further comprises:
• programmable physical media attachment (PMA) module operably coupled to transmit parallel data into transmit serial data in accordance with a programmed serialization setting of a corresponding one of the plurality of transceiver settings and to convert receive serial data into receive parallel data in accordance with a programmed deserialization setting of the corresponding one of the plurality of transceiver settings;
• programmable physical coding sublayer (PCS) module operably coupled to convert transmit data words into the transmit parallel data in accordance with a transmit PMA PCS interface setting of the corresponding one of the plurality of transceiver settings and to convert the receive parallel data into receive data words in accordance with a receive PMA PCS interface setting of the corresponding one of the plurality of transceiver settings;
• and
• programmable interface operably to convey the receive data words from the programmable PCS module to the programmable logic fabric section and the convey the transmit data words from the programmable logic fabric section to the programmable PCS module in accordance with a programmed logic interface setting, wherein the control module generates the programmed serialization setting, the programmed deserialization setting, the receive PMA PCS interface setting, the transmit PMA PCS interface setting, and the logic interface setting based on a desired mode of operation for the programmable multi-gigabit transceiver;
• wherein the programmable PCS module further comprises:
• a programmable PCS receive module operably coupled to convert the receive parallel data into the receive data words in accordance with the receive PMA PCS interface setting;
• and
• a programmable PCS transmit module operably coupled to convert the transmit data words into the transmit parallel data in accordance with the transmit PMA PCS interface setting;
• and
• wherein the programmable PCS receive module further comprises:
• programmable data alignment module operably coupled to align the receive parallel data in accordance with the receive PMA PCS interface setting to produce aligned data words, wherein size and rate of the aligned data words are set based on the receive PMA PCS interface setting;
• programmable descramble and decode module operably coupled to descramble, decode, or pass the aligned data words in accordance with the receive PMA PCS interface setting to produce processed aligned data words, wherein the receive PMA PCS interface setting indicates descrambling, decoding, or passing of the aligned data words, wherein the receive PMA PCS interface setting further indicates a type of descrambling when the programmable descramble and decode module is descrambling the aligned data words and further indicates a type of decoding when the programmable descramble and decode module is decoding the aligned data words;
• programmable storage module operably coupled to elastic store or pass the processed data words in accordance with the receive PMA PCS interface setting to produce stored data words;
• and
• programmable decode and verity module operably coupled to decode, verify or pass the stored data words in accordance with the receive PMA PCS interface setting and the programmed logic interface setting to produce the receive data words, wherein the receive PMA PCS interface setting indicates the decoding, the verifying or the passing of the stored data words, indicates a second type of decoding when the programmable decode and verity module is decoding the stored data words and indicates a type of verifying when the programmable decode and verify module is verifying the stored data words and wherein the programmed logic interface setting indicates rate and size of the received data words.