Bi-directional single wire interface
AssigneeAtmel Corporation
InventorsGabriel Rocas, Nathalie Delage
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Abstract
A single-wire, bi-directional communication protocol is provided in which the sending device transmits its clock frequency and its bit transmission period and data through a predefined waveform pattern or “learning sequence” that is recognizable by the receiving device and in a period of time, as measured in number of sending clock cycles, that is known to the receiving device. By clocking the full length of the predefined waveform pattern using its own internal clock, the receiving device becomes aware of the bit transmission period of the sending device.
Claims23
A method for carrying out bi-directional single-wire data communication between a first and a second device, each of which having a clock running at an independent frequency, comprising the steps of:
- a) having the first device send a learning sequence with a predetermined waveform pattern and a predetermined duration that represents a length of time, based on the clock in the first device, for transmitting a single bit to the second device;
- b) receiving the learning sequence by the second device, and analyzing the learning sequence to discover the clock frequency of the first device;
- and
- c) adjusting a sampling frequency based upon the discovered clock frequency.
A method for carrying out bi-directional single wire data communication between a master device having a clock running at a first frequency and a slave device having a clock running at a second frequency, wherein the steps of reading data from the slave device by the master device comprising:
- a) having the master device send a first command sequence that notifies the slave device of an intent to read;
- b) having the slave device send, in response, a learning sequence with a predetermined waveform pattern and a predetermined duration that represents a length of time, based on the clock in the slave device, for transmitting a single bit;
- c) initiating in the master device a counting routine wherein a duration, in number of clock cycles, of the learning sequence is measured based on the clock in the master device.
Dependencies are inferred from the claim text.