US 7,406,046 B2Granted

Scheduler for signaling a time out

AssigneeInfineon Technologies AG

InventorLorenzo Di Gregorio

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Abstract

A buffer storage memory data scheduler includes a write unit writing data objects to the memory, which unit receives data packets from a data source at a variable transmission rate, calculates attribute data for each received packet, and writes the packet data to the memory as a data object string including linked data objects. The string includes pointer data for linking the objects, calculated attribute data, and packet payload data. The write unit inserts filling objects into the memory between linked data objects to compensate for the variable rate when writing the string to the memory. The write unit increments a counter when the string is written. A time out signaling unit signals to a data processing unit that a buffer-stored data/filling object is ready to be read when the counter reaches a value. The signaling unit decrements the counter corresponding to the data in the object.

Claims34

Dependent claims

A scheduler for a memory system for buffer storage of data processed by at least one data processing unit, comprising:

a write unit for writing data objects to the memory system, said write unit:
receiving data packets from at least one data source at a variable data transmission rate, the data packets having payload data;
calculating attribute data for each received data packet;
writing the data contained in the data packet to the memory system as a data object string including data objects linked to one another, the data object string including pointer data for linking the data objects, the attribute data calculated, and the payload data;
and
inserting filling objects into the memory system between the data objects linked to one another to compensate for the variable data transmission rate when writing the data object string to the memory system;
a counter connected to said write unit and incremented by said write unit when the data object string is written to the memory system to correspond to an amount of data contained in the data packet and the filling data in the tilling objects;
a time out signaling unit connected to said counter, said time out signaling unit:
signaling, when said counter reaches a threshold value, to the data processing unit that at least one of the data object and the filling object buffer stored in the memory system is ready to be read;
and
subsequently decrementing said counter corresponding to the data contained in the data object provided;
said write unit having a control path and a data path;
said data path having a counting device incremented linearly in accordance with a linear nominal data arrival curve;
and
said data path having an effective data address generator calculating a time wheel distribution as a function of a calculated cumulative amount of data and of a count produced by the counting device, as follows:
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where R(t) is an amount of data in a received data packet, and α is the linear nominal data arrival curve.

101 more elements

A scheduler for a memory system for buffer storage of data processed by at least one data processing unit, comprising:

a write unit for writing data objects to the memory system, said write unit:
receiving data packets from at least one data source at a variable data transmission rate, the data packets having payload data;
calculating attribute data for each received data packet;
writing the data contained in the data packet to the memory system as a data object string including data objects linked to one another, the data object string including pointer data for linking the data objects, the attribute data calculated, and the payload data;
and
inserting filling objects into the memory system between the data objects linked to one another to compensate for the variable data transmission rate when writing the data object string to the memory system;
a counter connected to said write unit and incremented by said write unit when the data object string is written to the memory system to correspond to an amount of data contained in the data packet and the filling data in the tilling objects;
a time out signaling unit connected to said counter, said time out signaling unit:
signaling, when said counter reaches a threshold value, to the data processing unit that at least one of the data object and the filling object buffer-stored in the memory system is ready to be read;
and
subsequently decrementing said counter corresponding to the data contained in the data object provided;
said write unit having a control path and a data path;
said data path having a basic address register bank including at least two basic address registers;
and
one of said basic address registers being provided for each data source;
and
said data path having:
a FIFO memory;
and
a FIFO control unit connected to said FIFO memory for writing and reading data to and from said FIFO memory;
said FIFO control unit records the cumulative amount of payload data of the payload data in a data packet;
and
an initial address of the data object is written to said basic address register whenever there is a change to the calculated cumulative amount of payload data.

20 more elements

A scheduler for a memory system for buffer storage of data processed by at least one data processing unit, comprising:

a write unit for writing data objects to the memory system, said write unit:
receiving data packets from at least one data source at a variable data transmission rate, the data packets having payload data;
calculating attribute data for each received data packet;
writing the data contained in the data packet to the memory system as a data object string including data objects linked to one another, the data object string including pointer data for linking the data objects, the attribute data calculated, and the payload data;
and
inserting filling objects into the memory system between the data objects linked to one another to compensate for the variable data transmission rate when writing the data object string to the memory system;
a counter connected to said write unit and incremented by said write unit when the data object string is written to the memory system to correspond to an amount of data contained in the data packet and the filling data in the filling objects;
a time out signaling unit connected to said counter, said time out signaling unit:
signaling, when said counter reaches a threshold value, to the data processing unit that at least one of the data object and the filling object buffer-stored in the memory system is ready to be read;
and
subsequently decrementing said counter corresponding to the data contained in:
the data object provided;
said write unit having a control path and a data path;
said data path having:
a FIFO memory;
and
a FIFO control unit connected to said FIFO memory for writing and reading data to and from said FIFO memory;
said data path having a data multiplexer for writing data to the memory system and an address multiplexer for supplying an address to the memory system;
said data path having a basic address register bank including at least two basic address registers;
one of said basic address registers is provided for each data source;
and
said data multiplexer having:
a first input connected to said FIFO memory, said first input receiving the attribute and payload data read from said FIFO memory;
and
a second input connected to said base address register bank, said second input receiving the linking data.

22 more elements

Dependencies are inferred from the claim text.