System and method to synchronize signals in individual integrated circuit components
AssigneeInfineon Technologies AG
InventorsAlessandro Minzoni, Jonghee Han
Life of this patent
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Abstract
A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.
Claims27
A method of synchronizing an output signal generated by an integrated circuit (IC) component to a clock signal applied to the component, comprising:
- incrementally altering a variable feedback delay in the IC component to alter the phase skew between the clock signal and the output signal;
- monitoring in the IC component the relative phase order of the clock and output signals;
- and
- ceasing to alter the variable feedback delay in response to detecting a swap in the relative phase order of the clock and output signals.
An integrated circuit (IC) component, comprising:
- a Delay Locked Loop (DLL) circuit operative to synchronize internal clock signals to an applied external clock input;
- a signal generation circuit connected to the DLL circuit and operative to generate an output signal synchronous with the external clock input;
- a monitoring circuit operative to detect the relative phase order between the output signal and the clock input;
- and
- a control circuit operative to alter a variable feedback delay of the DLL circuit until the monitoring circuit indicates a swap in the relative phase order between the output signal and the clock input.
An integrated circuit (IC) component, comprising:
- an input buffer to receive an applied clock signal;
- an output buffer to drive a synchronous output signal;
- a signal generation circuit operative to generate the synchronous output signal;
- a Delay Locked Loop including a variable feedback delay, the delay of which alters the phase skew between the clock and output signals;
- a phase detector receiving the clock signal prior to the input buffer and receiving the output signal after the output buffer, and outputting a signal indicative of the relative phase order of the clock and output signals;
- and
- synchronization logic operative to incrementally alter the variable feedback delay, and to synchronize the clock and output signals by ceasing to alter the variable feedback delay when the phase detector output indicates a swap in the relative phase order of the clock and output signals.
A method of manufacturing integrated circuit (IC) components, comprising:
- for each individual IC component on a wafer, synchronizing an output signal to an applied clock input signal by determining a value for a variable feedback delay in a Delay Locked Loop in the IC component that substantially phase aligns the clock and output signals;
- and
- blowing one or more fuses on the IC component to set the variable feedback delay to the determined value.
An integrated circuit (IC) component, comprising:
- input buffering means for receiving an applied clock signal;
- output buffering means for driving a synchronous output signal;
- a Delay Locked Loop including a variable feedback delay, the delay of which alters the phase skew between the clock and output signals;
- phase detecting means receiving the clock signal prior to the input buffer and receiving the output signal after the output buffer, for determining the relative phase order of the clock and output signals;
- and
- synchronizing means for incrementally altering the variable feedback delay, and for synchronizing the clock and output signals by ceasing to alter the variable feedback delay when the phase detecting means detects a swap in the relative phase order of the clock and output signals.
Dependencies are inferred from the claim text.