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US 7,405,994 B2Granted
Dual port cell structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
Estimating the term…
Abstract
Disclosed are improved layouts for memory cell and memory cell arrays. A memory cell array of multiple memory cells connected by signal lines that twist in connecting the array. Further, an eight transistor memory cell that comprises different resistive paths as seen by the signal lines electrically connected to the cell and asymmetric pass devices associated with those resistive paths. Furthermore, an eight transistor memory cell that includes butt contacts.
Claims21
A memory circuit comprising:
- an array of memory cells arranged in one or more rows and one or more columns, wherein each row and each column comprises a plurality of memory cells;
- at least two signal lines extending along each column of memory cells, each of the two signal lines being electrically connected to first and second terminals of each memory cell in the column;
- and
- a cross-sectional area associated with each row, wherein the two signal lines in a first column twist in a first cross-sectional area, wherein the signal lines are bit lines, the memory cells are dual ported, and each column comprises at least two additional bit lines electrically connected to a third and fourth terminal of each cell in the column.
1 more element
A memory circuit comprising:
- an array of dual port memory cells arranged in one or more rows and one or more columns, wherein each row and each column comprises a plurality of memory cells;
- at least two bit lines extending along each column of memory cells, each of the two bit lines being electrically connected to first and second terminals of each memory cell in the column;
- at least two additional bit lines electrically connected to a third and fourth terminal of each cell in the column;
- a cross-sectional area associated with each row, wherein two bit lines in a first column twist in a first cross-sectional area;
- and
- at least two word lines per row, the first word line being electrically connected to a fifth terminal of each cell in the row, the second word line being electrically connected to a sixth terminal of each cell in the row.
3 more elements
A dual-ported eight transistor memory cell comprising:
- four pass transistors, two pull-up transistors, and two pull-down transistors wherein the connection path between the source node of a first pass transistor and a first pull-down device is a structure of a first resistance and the connection path between the source node of a second pass transistor and a second pull-down device is a structure of a second resistance, wherein the structure of a first resistance is of greater resistance than the structure of a second resistance, and said first and second pass transistors are asymmetrical;
- four bit lines each electrically connected to one of the pass transistors;
- and
- first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors.
1 more element
A dual-ported eight transistor memory cell comprising:
- four pass transistors, two pull-up transistors, and two pull-down transistors, a first butt contact for connecting a first pass transistor and one of the pull-up or pull-down transistors, and a second butt contact connecting a second pass transistor with a second one of the pull-up or pull-down transistors;
- first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors;
- and
- four bit lines, each connecting to one of the pass transistors.
1 more element
A dual-ported eight transistor memory cell comprising:
- four pass transistors, two pull-up transistors, and two pull-down transistors, a first butt contact for connecting a first pass transistor and one of the pull-up or pull-down transistors, and a second butt contact connecting a second pass transistor with a second one of the pull-up or pull-down transistors, a third and fourth butt contact connecting the pull-up or pull-down transistors, and wherein the connection path between a first pass transistor and a first pull-down device is a structure of a first resistance and the connection path between the second pass transistor and a second pull-down device is a structure of a second resistance wherein the structure of a first resistance is of greater resistance than the structure of a second resistance;
- first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors;
- and
- four bit lines, each connecting to one of the pass transistors.
1 more element
A dual-ported eight transistor memory cell comprising:
- four pass transistors, two pull-up transistors, and two pull-down transistors, a first butt contact for connecting a first pass transistor and one of the pull-up or pull-down transistors, and a second butt contact connecting a second pass transistor with a second one of the pull-up or pull-down transistors and a third and fourth butt contact connecting the pull-up or pull-down transistors;
- first and second word lines, the first word line connecting to a first electrode of two of the pass transistors, the second word line connecting to a first electrode of the other two pass transistors;
- and
- four bit lines, each connecting to one of the pass transistors,
- wherein the butt contacts are standalone holes connecting an active region to a gate layer with no metal layer directly connected to the butt contacts.
2 more elements
A memory circuit comprising:
- an array of dual port memory cells arranged in rows and columns, wherein each row and each column comprises a plurality of memory cells, wherein at least one of the dual port memory cells comprises a first connection path between a first pass transistor and a first pull-down transistor having a first resistance and a second connection path between a second pass transistor and a second pull-down transistor having a second resistance, wherein the first resistance is greater than the second resistance;
- and
- at least two signal lines extending along each column of dual port memory cells, and electrically connected to a plurality of dual port memory cells, wherein the at least two signal lines in a first column twist in a first cross-sectional area.
A dual-ported memory cell comprising:
- a first connection path between a first pass transistor and a first pull-down transistor having a first resistance;
- a second connection path between a second pass transistor and a second pull-down transistor having a second resistance, wherein the first resistance is greater than the second resistance.
Dependencies are inferred from the claim text.