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US 7,405,992 B2Granted
Method and apparatus for communicating command and address signals
AssigneeQimonda North America Corp.
InventorJong-Hoon Oh
Life of this patent
Estimating the term…
Abstract
Apparatus and methods for communicating command and address inputs to a memory device. In one embodiment, a memory device includes a shared bus interface defined by a portion of pins from a command bus interface and a portion of pins from an address bus interface. Each portion of pins is configured to receive address and command inputs, depending a given command/address combination being asserted by a memory controller.
Claims18
A device, comprising:
- a command bus interface comprising one or more command pins dedicated to receiving command inputs and one or more shared pins for selectively receiving address inputs and command inputs;
- and
- an address bus interface comprising one or more address pins dedicated to receiving address inputs and one or more shared pins for selectively receiving address inputs and command inputs.
A memory device, comprising:
- a command bus interface comprising one or more command pins dedicated to receiving command inputs and one or more shared pins for selectively receiving address inputs and command inputs;
- an address bus interface comprising one or more address pins dedicated to receiving address inputs and one or more shared pins for selectively receiving address inputs and command inputs;
- a pre-decoder communicatively coupled to the one or more command pins and configured to decode control inputs received on the one or more command pins into a plurality of command type signals;
- a first command decoder receiving as inputs a first one of the plurality of command type signals and one or more command inputs from the shared pins of the command bus interface and the address bus interface;
- and
- a second command decoder receiving as inputs a second one of the plurality of command type signals and one or more command inputs from the shared pins of only the command bus interface.
3 more elements
A memory device, comprising:
- a command bus interface comprising one or more command pins dedicated to receiving command inputs and one or more shared pins for selectively receiving address inputs and command inputs;
- an address bus interface comprising one or more address pins dedicated to receiving address inputs and one or more shared pins for selectively receiving address inputs and command inputs;
- a pre-decoder communicatively coupled to the one or more command pins and configured to decode control inputs received on the one or more command pins into a plurality of command type signals;
- a first command decoder receiving as inputs a first one of the plurality of command type signals and one or more command inputs from the shared pins of the command bus interface and the address bus interface;
- a second command decoder receiving as inputs a second one of the plurality of command type signals and one or more command inputs from the shared pins of only the command bus interface;
- an address decoder coupled to the shared pins of the command bus interface and the address bus interface;
- a first driver disposed on a first signal path coupling the address decoder to the command bus interface, the first driver being enabled by the first one of the plurality of command type signals;
- and
- a second driver disposed on a first signal path coupling the address decoder to the address bus interface, the second driver being enabled by the second one of the plurality of command type signals.
6 more elements
An apparatus, comprising:
- a memory controller configured to assert a plurality of address/command combinations each comprising a plurality of address inputs and command inputs;
- and
- a memory device, comprising:
- a command bus interface comprising one or more command pins dedicated for receiving command inputs and one or more shared pins for selectively receiving address inputs and command inputs, the command bus interface coupled to the memory controller by a command bus;
- and
- an address bus interface comprising one or more address pins dedicated for receiving address inputs and one or more shared pins for selectively receiving address inputs and command inputs, the address bus interface coupled to the memory controller by a address bus.
3 more elements
Dependencies are inferred from the claim text.