Flash memory device with improved read speed
AssigneeSamsung Electronics Co., Ltd.
InventorsDoo-Sub Lee, Heung-Soo Lim
Life of this patent
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Abstract
A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.
Claims18
A flash memory device, comprising:
- an array of multi-bit memory cells arranged in rows and columns;
- a row selecting circuit comprising first, second, and third voltage lines, wherein the row selecting circuit selects a word line indicated by a read address and drives the selected word line with a word line voltage;
- a word line voltage generating circuit generating first, second, and third read voltages and respectively supplying the first, second, and third read voltages to the first, second and third voltage lines before the row selecting circuit selects the word line indicated by the read address;
- wherein the first, second, and third voltage lines respectively and sequentially apply the first, second, and third read voltages to the word line indicated by the read address as the word line voltage during a read operation.
A flash memory device adapted to store multi-bit data, the device comprising:
- a memory cell array including a columnar arrangement of banks, each of the banks being addressed by a plurality of word lines;
- at least one row selecting circuit selecting one of the plurality of word lines in response to a read address;
- a plurality of decoding and driving blocks corresponding to the plurality of banks, respectively, each decoding and driving block comprising first, second, and third voltage line segments, and driving the selected word line with a word line voltage;
- a word line voltage generating circuit generating first, second, and third read voltages;
- first, second, and third voltage lines traversing the columnar arrangement of banks and simultaneously applying the first, second and third read voltages to the plurality of decoding and driving blocks before the row selecting circuit selects the word line in response to the read address.
A row selecting circuit for a flash memory device, comprising;
- a memory cell array having multi-bit memory cells arranged in rows and columns, a word line voltage generating circuit generating first, second, and third read voltages, and control logic, wherein the row selecting circuit comprises;
- decoder circuitry decoding a read address and selecting a word line in response to the read address;
- first, second, and third voltage lines respectively receiving the first, second, and third read voltages from the word line voltage generating circuit before the decoder circuitry selects the word line during a multi-bit read operation;
- a selector sequentially selecting between the first, second, and third voltage lines in response to control signals provided by the control logic;
- a switch sequentially outputting the first, second, and third read voltages received from the first, second, and third voltage lines by operation of the selector in response to an output of the decoder circuitry;
- and,
- a word line driver sequentially driving the selected word line with the first, second, and third read voltages output by the switch during first, second, and third read periods.
Dependencies are inferred from the claim text.