US 7,405,974 B2 · Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device

Abstract

A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

Claims64

Dependent claims

A semiconductor memory device, comprising:

a memory array of memory elements each including:
a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;
a page buffer circuit connected to a main bus via a first port and to an internal bus via a second port, containing multiple page planes;
an access control circuit operating either in a user mode or in a memory control mode as determined by a control signal, enabling access to the page planes over the main bus when in the user mode and over the internal bus when in the memory control mode;
an interface circuit connected to the main bus and the page buffer circuit, generating the control signal to assign the page planes to the user mode and the memory control mode in accordance with a command received over the main bus;
and
a memory control circuit controlling at least write operation to the memory array, connected to the page buffer circuit over the internal bus and accessing the page buffer circuit in the memory control mode.

8 more elements

A page buffer resource assign method of assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrode, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;
said method comprising the steps of:
receiving a rewrite page buffer continuous command over a main bus and assigning a first page plane to a user mode so as to enable access to the first page plane over the main bus in the user mode, the first page plane being provided in a page buffer resource connected to the main bus via a first port and to an internal bus via a second port;
receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;
receiving a program containing a page buffer command and assigning the first page plane to a memory control mode so as to enable a memory control circuit to access the first page plane in the memory control mode over the internal bus;
and
when a second page plane in the page buffer resource is not assigned to the memory control mode, assigning the second page plane to the user mode.

8 more elements

A page buffer resource assign method of assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrode, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;
said method comprising the steps of:
the page buffer resource receiving a rewrite page buffer continuous command over a main bus, the page buffer resource including a first page plane and a second page plane and connected to the main bus via a first port and to an internal bus via a second port;
assigning the first page plane to a user mode so as to enable access to the first page plane over the main bus in the user mode;
receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;
receiving a program containing a page buffer command and assigning the first page plane to a memory control mode according to the program so as to enable a memory control circuit to internally access the first page plane in the memory control mode;
and
receiving a swap page buffer command over the main bus and swapping the user mode and the memory control mode between the first page plane and the second page plane.

9 more elements

A page buffer resource assign circuit assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;
the page buffer circuit being connected to a main bus via a first port and to an internal bus via a second port;
the page buffer resource assign circuit comprising an assign control circuit:
(1) receiving a rewrite page buffer continuous command over the main bus and assigning a first page plane to a user mode so as to enable access to the first page plane in the page buffer resource over the main bus in the user mode;
(2) receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;
(3) receiving a program containing a page buffer command and assigning the first page plane to a memory control mode according to the program so as to enable a memory control circuit to access the first page plane in the memory control mode over the internal bus;
and
(4) when a second page plane in the page buffer resource is not assigned to the memory control mode, assigning the second page plane to the user mode.

9 more elements

A page buffer resource assign circuit assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;
the page buffer circuit being connected to a main bus via a first port and to an internal bus via a second port;
the page buffer resource assign circuit comprising an assign control circuit:
(1) receiving a rewrite page buffer continuous command over the main bus and assigning a first page plane to a user mode so as to enable access to the first page plane in the page buffer resource over the main bus in the user mode;
(2) receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;
(3) the assign control circuit receiving a program containing a page buffer command and assigning the first page plane to a memory control mode so as to enable a memory control circuit to access the first page plane in the memory control mode over the internal bus;
and
(4) receiving a swap page buffer command over the main bus and swapping the user mode and the memory control mode between the first page plane and a second page plane over the main bus according to the according to swap page buffer command.

9 more elements

A computer system, comprising:

a central processing unit transferring a command and a rewrite data block over a main bus;
and
a semiconductor memory device including a memory array of memory elements and a page buffer resource,
the memory elements each including:
a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held,
the page buffer resource being connected to the main bus via a first port and to an internal bus via a second port, wherein:
the semiconductor memory device receives the command over the main bus, assigning the page buffer resource in accordance with the command, and receives and buffers a rewrite data block in the page buffer resource while writing another rewrite data block to the memory array;
and
the semiconductor memory device including:
a memory control circuit connected to the internal bus, controlling at least write operation to the memory array;
and
an interface circuit connected to the main bus and the page buffer resource, receiving a command over the main bus and generating a control signal to assign page planes in the page buffer resource to a user mode and a memory control mode in accordance with the received command.

13 more elements

A computer system, comprising:

a central processing unit transferring a command and a rewrite data block over a main bus;
and
a semiconductor memory device including a memory array of memory elements and a page buffer resource,
the memory elements each including:
a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held,
the page buffer resource being connected to the main bus via a first port and to an internal bus via a second port, wherein
the semiconductor memory device includes an assign control circuit:
(1), being connected to the main bus and the second port, receiving a command and assigning the page buffer resource to receive and buffer the rewrite data block while writing another rewrite data block to the memory array;
(2) receiving the rewrite data block over the main bus and transferring the rewrite data block to a first page plane in the page buffer resource;
(3) receiving a rewrite page buffer continuous command over the main bus and assigning the first page plane to a user mode so as to enable access to the first page plane over the main bus in the user mode;
(4) receiving a program including a page buffer command and assigning the first page plane to a memory control mode according to the program so as to enable a memory control circuit to access the first page plane over the internal bus in the memory control mode;
and
(5) if a second page plane in the page buffer resource is not assigned to the memory control mode, assigning the second page plane to the user mode.

14 more elements

A computer system, comprising:

a central processing unit transferring a command and a rewrite data block over a main bus;
and
a semiconductor memory device including a memory array of memory elements and a page buffer resource,
the memory elements each including:
a gate electrode provided on a semiconductor layer with an intervening gate insulating film;
a channel region provided beneath the gate electrode;
a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region;
and
a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held, the page buffer resource being connected to the main bus via a first port and to an internal bus via a second port, having a first page plane and a second page plane, wherein
the semiconductor memory device includes an assign control circuit:
(1), being connected to the main bus and the second port, receiving a command and assigning the page buffer resource to receive and buffer the rewrite data block while writing another rewrite data block to the memory array;
(2) receiving a rewrite page buffer continuous command over the main bus and assigning the first page plane to a user mode so as to enable access to the first page plane in the page buffer resource over the main bus in the user mode;
(3) receiving the rewrite data block over the main bus and transferring the rewrite data block to the first page plane;
(4) receiving a program including page buffer command and assigning the first page plane to a memory control mode according to the program.

11 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device

Life of this patent

Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device

Life of this patent

Abstract

Claims64