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US 7,405,970 B2Granted
Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
AssigneeKabushiki Kaisha Toshiba
InventorsTomoharu Tanaka, Jian Chen
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Abstract
A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
Claims22
A non-volatile semiconductor memory device comprising:
- a plurality of electrically data rewritable non-volatile semiconductor memory cells;
- a memory cell array in which a plurality of the memory cells or memory cell units are arranged in matrix, the memory cell unit including at least one of the memory cells;
- a plurality of word lines connected to gates of the memory cells;
- a write circuit configured to write data in a plurality of selected memory cells in the memory cells, the write circuit writes a data in the plurality of selected memory cells by supplying a write voltage and a write control voltage to the plurality of selected memory cells,
- a first memory cell included in the memory cells;
- a second memory cell included in the memory cells;
- and
- a third memory cell included in the memory cells, gates of the first memory cell, the second memory cell and the third memory cells being connected to a first word line,
- wherein there are plurality of distributions of threshold value of the memory cells, the plurality of distributions of threshold value includes a first distribution of threshold value and a second distribution of threshold value, the second distribution of threshold value has higher threshold values than the first distribution of threshold value, the write voltage is divided into plurality of pulses, the write voltage increases with a stepwise increment of predetermined voltage per pulse in two or more ones of the plurality of pulses, a first write control voltage, a second control voltage and a third write control voltage are respectively supplied to the first memory cell, the second memory cell and the third memory cell while at least one pulse of the write voltage is supplied to a first word line, all of the first memory cell, the second memory cell and the third memory cell are included in the second distribution of threshold value after the plurality of pulses are supplied to the first word line, and the first write control voltage, the second control voltage and the third control voltage are different one another.
6 more elements
A non-volatile semiconductor memory device comprising:
- a plurality of electrically data rewritable non-volatile semiconductor memory cells;
- a plurality of word lines connected to gates of the memory cells;
- a write circuit configured to write data in a plurality of selected memory cells in the memory cells, the write circuit writes a data in the plurality of selected memory cells by supplying a write voltage and a write control voltage to the plurality of selected memory cells;
- a first memory cell included in the memory cells;
- a second memory cell included in the memory cells;
- and
- a third memory cell included in the memory cells, gates of the first memory cell, the second memory cell and the third memory cells being connected to a first word line,
- wherein a first step operation, a second step operation and a third step operation are conducted sequentially when the write circuit writes a data in the plurality of selected memory cells, a first write control voltage, a second control voltage and a third control voltage are respectively supplied to the plurality of the selected memory cells in the first step operation, the second step operation and the third step operation, the first write control voltage, the second control voltage and the third control voltage are different one another, the write voltage is divided into plurality of pulses, the write voltage increases with a stepwise increment of predetermined voltage per pulse, the first step operation, the second step operation and the third step operation are respectively performed for the first memory cell, the second memory cell and the third memory cell in the same time while at least one pulse of the write voltage is supplied to a first word line.
5 more elements
Dependencies are inferred from the claim text.