Phase change memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsByung-gil Choi, Du-eung Kim, Woo-yeong Cho
Life of this patent
Estimating the term…
Abstract
A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.
Claims17
A phase change memory device comprising:
- a semiconductor substrate which includes a plurality of phase change memory cells;
- a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells;
- and
- a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines,
- wherein the plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.
A phase change memory device comprising:
- a semiconductor substrate including a plurality of phase change memory block regions and a plurality of column selection regions;
- a plurality of phase change memory cells formed in each of the plurality of phase change memory block regions;
- a plurality of local bit lines extending over the plurality of phase change memory block regions, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells;
- adjacent first and second global bit lines extending in a direction to cross over the plurality of phase change memory block regions;
- and
- a plurality of column selection transistors formed on each of the plurality of column selection regions, each of the plurality of column selection transistors coupled between each of the plurality of local bit lines and the first or second global bit line,
- wherein the first and second global bit lines are located at different wiring line levels over the semiconductor substrate.
A phase change memory device comprising:
- a semiconductor substrate including a plurality of phase change memory block regions and a plurality of column selection regions;
- a plurality of phase change memory cells formed in each of the plurality of phase change memory block regions;
- a plurality of local bit lines extending over the plurality of phase change memory block regions, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells;
- a plurality of global bit lines including a first and second global bit line extending in a direction to cross over the plurality of phase change memory block regions;
- and
- a plurality of column selection transistors formed in each of the plurality of column selection regions, each of the plurality of column selection transistors being coupled between each of the plurality of local bit lines and the first or second global bit line,
- wherein each of the plurality of global bit lines is formed of a plurality of metal wiring lines that are formed at two or more wiring line levels and are coupled to each other.
Dependencies are inferred from the claim text.