Integrated circuit to identify read disturb condition in memory cell
AssigneeQimonda North America Corp.
InventorsJan Boris Philipp, Thomas Happ
Life of this patent
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Abstract
A method of operating a phase change memory array is disclosed and includes identifying a read disturb condition associated with the phase change memory array, and performing a conditional refresh operation in response to the identified read disturb condition. A phase change memory is also disclosed and includes an array of phase change memory cells, and a read disturb system configured to identify a read disturb condition and perform a refresh operation on the array in response thereto.
Claims23
A method of operating a resistivity changing memory cell, comprising:
- reading a resistivity changing sensor memory cell with a read operation that is different than a read operation associate with the resistivity changing memory cell;
- identifying a read disturb condition associated with the resistivity changing memory cell if the different read operation caused a disturbance of data in the read resistivity changing sensor memory cell;
- and
- performing a refresh operation in response to the identified read disturb condition.
A method of operating a phase change memory array, comprising:
- sensing a read disturb condition;
- and
- performing a refresh operation when the read disturb condition is sensed,
- wherein sensing the read disturb condition comprises:
- programming a read disturb phase change memory cell to the reset state;
- performing a read disturb read operation on the read disturb phase change memory cell with a read operation that is different than a read operation associated with a phase change memory cell;
- and
- determining whether the read disturb condition exists based on whether the read disturb operation caused the read disturb phase change memory cell to have a resistance lower than a predetermined value.
A method of operating a multi-bit phase change memory array, comprising:
- sensing a read disturb condition associated with one of the multiple available states of a multi-bit phase change memory cell;
- and
- performing a refresh operation when the read disturb condition is sensed;
- wherein sensing a read disturb condition includes reading a phase change sensor memory cell with a read operation that is different than a read operation associate with the multi-bit phase change memory cell, and sensing the read disturb condition if the different read operation caused a disturbance of data in the phase change sensor memory cell.
An integrated circuit, comprising:
- a resistivity changing memory cell;
- and
- a read disturb system configured to identify a read disturb condition and perform a refresh operation on the memory cell in response thereto,
- wherein the read disturb system is configured to identify the read disturb condition by reading a resistivity changing sensor memory cell with a read operation that is different than a read operation associated with the resistivity changing memory cell, and identifying the read disturb condition if the different read condition caused a disturbance of data in the read resistivity changing sensor memory cell.
A phase change memory system, comprising:
- an array of phase change memory cells;
- a phase change memory read sensor;
- a refresh controller configured to perform a refresh operation on the array of phase change memory cells when the read sensor indicates a read disturb condition;
- and
- a pulse generator configured to generate and provide a read disturb signal to the phase change memory read sensor.
A phase change memory system, comprising:
- an array of phase change memory cells;
- a phase change memory read sensor;
- a refresh controller configured to perform a refresh operation on the array of phase change memory cells when the read sensor indicates a read disturb condition;
- and
- a sense amplifier configured to sense a state of the phase change memory read sensor during a read operation, and communicate the sensed state to the refresh controller.
A phase change memory system, comprising:
- an array of phase change memory cells;
- and
- means for detecting a read disturb condition associated with the array and performing a refresh operation in response thereto,
- the means for detecting further comprising:
- means for reading a resistively changing sensor memory cell with a read operation that is different than a read operation associated with the resistively changing memory cell, and
- means for identifying the read disturb condition if the different read condition caused a disturbance of data in the read resistively changing sensor memory cell.
Dependencies are inferred from the claim text.