Ferroelectric memory device
AssigneeSeiko Epson Corporation
InventorsYasunori Koide, Hiroyoshi Ozeki
Life of this patent
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Abstract
A ferroelectric memory device includes memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines. The ferroelectric memory device includes: first and second local bit lines associated with a first main bit line; first and second connection transistors for connecting the first and second local bit lines to the first main bit line; first and second grounding transistors for grounding the first and second local bit lines; a first selection line that is commonly connected to gates of the first grounding transistor and the second connection transistor; and a second selection line that is commonly connected to gates of the first connection transistor and the second grounding transistor.
Claims8
A ferroelectric memory device having memory cells using ferroelectric capacitors provided at intersections of local bit lines associated with a main bit line and word lines, the ferroelectric memory device comprising:
- first and second local bit lines associated with a first main bit line;
- first and second connection transistors for connecting the first and second local bit lines to the first main bit line;
- first and second grounding transistors for grounding the first and second local bit lines;
- a first selection line that is commonly connected to gates of the first grounding transistor and the second connection transistor;
- and
- a second selection line that is commonly connected to gates of the first connection transistor and the second grounding transistor.
Dependencies are inferred from the claim text.