Negative contributive offset compensation in a transmit buffer utilizing inverse clocking

A digital to radio frequency (RF) amplitude converter apparatus, comprising:

• a plurality of transistors coupled to positive outputs and negative outputs generated by a sigma-delta modulator;
• first means for driving transistors coupled to said positive outputs using a clock signal;
• second means for driving transistors coupled to said negative outputs using an inverted version of said clock signal;
• and
• third means for summing the output of each transistor to yield an offset compensated output signal.

A transmit buffer, comprising:

• a plurality of gates arranged in a parallel array, wherein a first portion of said gates are coupled to one or more positive outputs generated by a sigma-delta modulator, a second portion of said gates are coupled to one or more negative outputs generated by said sigma-delta modulator;
• first means for driving the gates coupled to said positive outputs with a clock signal;
• second means for driving the gates coupled to said negative outputs with an inverted version of said clock signal;
• a plurality of transistors, the output of each gate coupled to one of said transistors;
• and
• a matching network coupled to the output of each transistor and operative to generate an offset compensated radio frequency (RF) output signal.

A digital to radio frequency (RF) amplitude converter apparatus, comprising:

• a plurality of switches coupled to positive outputs and negative outputs generated by a digital modulator;
• first means for driving a portion of said switches coupled to said positive outputs with a clock signal;
• second means for driving a second portion of said switches coupled to said negative outputs with an inverted version of said clock signal;
• and
• third means for summing the output of each switch to yield an output signal.

A digital to radio frequency (RF) amplitude converter apparatus, comprising:

• a plurality of switches coupled to positive outputs and negative outputs generated by a digital modulator;
• first means for driving a first portion of said switches coupled to said positive outputs with a clock signal;
• second means for driving a second portion of said switches coupled to said negative outputs with a different phase of said clock signal;
• and
• third means for summing the output of each switch to yield an output signal.

A method of offset compensation in a digital to radio frequency (RF) amplitude converter (DRAC), said method comprising the steps of:

• coupling a plurality of transistors to positive outputs and negative outputs generated by a sigma-delta modulator;
• coupling first driving transistors to said positive outputs using a clock signal;
• coupling second driving transistors to said negative outputs using a different phase of said clock signal;
• and
• summing outputs of said plurality of transistors to yield an offset compensated output signal.

A method of offset compensation in a digital to radio frequency (RF) amplitude converter (DRAC), said method comprising the steps of:

• coupling respective ones of a first plurality of transistors to respective positive outputs of a modulator;
• coupling respective ones of a second plurality of transistors to respective negative outputs of said modulator;
• a first clock signal enabling said first plurality of transistors;
• a second clock signal enabling said second plurality of transistors;
• and
• summing outputs of said first plurality of transistors and second plurality of transistors to yield an offset compensated output signal.

A transmit buffer, comprising:

• a plurality of gates arranged in a parallel array, wherein a first portion of said gates are coupled to one or more positive outputs generated by a sigma-delta modulator, a second portion of said gates are coupled to one or more negative outputs generated by said sigma-delta modulator;
• circuitry for driving the gates coupled to said positive outputs with a first clock signal;
• circuitry for driving the gates coupled to said negative outputs with a second clock signal;
• a plurality of transistors, an output of each gate coupled to one of said transistors;
• and
• a matching network coupled to the output of each transistor and operative to generate an offset compensated radio frequency (RF) output signal.

A digital to radio frequency (RF) amplitude converter apparatus, comprising:

• a plurality of switches coupled to positive and negative outputs generated by a digital modulator;
• circuitry for driving a first portion of said switches coupled to said positive outputs with a first clock signal;
• circuitry for driving a second portion of said switches coupled to said positive outputs with a first clock signal;
• a plurality of transistors, an output of each gate coupled to one said transistors;
• and
• circuitry for summing the output of each switch to yield an output signal.