Technique for switching between input clocks in a phase-locked loop
AssigneeSilicon Laboratories Inc.
InventorsRonald B. Hulfachor, Srisai R. Seethamraju, Shailesh Chitnis
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Abstract
A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.
Claims24
A method of switching between a first clock signal and a second clock signal being utilized as an input clock signal to a phase-locked loop (PLL), the method comprising:
- generating an output signal based at least in part on a pulsed phase-difference signal indicating a phase difference between a feedback signal of the PLL and the input clock signal;
- and
- injecting a pulsed phase-difference compensation signal into the PLL in response to switching the input clock signal from the first clock signal to the second clock signal.
An apparatus comprising:
- a phase-locked loop (PLL) coupled to generate an output signal based at least in part on a reference clock signal and coupled to switch between a first input clock signal and a second input clock signal as the reference clock signal, wherein the PLL comprises:
- a first phase detector and charge pump circuit coupled to detect a first phase difference between a first feedback signal and a clock signal that corresponds to the first input clock signal and coupled to generate a first pulsed phase-difference signal indicative thereof;
- and
- a first phase-difference compensation circuit coupled to generate a first pulsed phase-difference compensation signal in response to the first input clock signal being utilized as the reference clock signal, the first pulsed phase-difference compensation signal being indicative of the first phase difference when the second input clock signal was utilized as the reference clock signal prior to the first input clock signal being utilized as the reference clock signal.
An apparatus comprising:
- means for generating a phase-difference signal comprising a DC component and higher frequency components, the phase-difference signal indicating the phase difference between a first clock signal and a feedback signal of a PLL;
- and
- means for generating a phase-difference compensation signal in response to switching a reference clock signal of the PLL from the first clock signal to a second clock signal, the phase-difference compensation signal substantially attenuating the DC component of the phase-difference signal and at least partially attenuating the higher frequency components of the phase-difference signal.
Dependencies are inferred from the claim text.