US 7,405,611 B2Granted

Semiconductor integrated circuit device

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorMasaya Sumita

Life of this patent

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Abstract

To save power consumption in a semiconductor integrated circuit 2A increased due to a leak current caused by a variation in a manufacturing process, temperature, and a power supply voltage. A semiconductor integrated circuit 2A, a leak current detection circuit 3, a comparison operation circuit 4 and an applied voltage output circuit 5A are provided. The semiconductor integrated circuit 2A has a circuit body 21 including a plurality of functional MOSFETs for performing predetermined functional operations, and a monitor circuit 22A including a plurality of monitor NMOSFETs 23 for monitoring properties of the functional MOSFETs. The leak current detection circuit 3 detects leak data corresponding to leak currents from the monitor NMOSFETs 23, and outputs the detected leak data. The comparison operation circuit 4 extracts, from a plurality of pieces of leak data, one piece of leak data minimizing a leak current in the circuit body 21, and outputs the extracted leak data as applied voltage data. The applied voltage output circuit 5A sets and outputs a source-drain voltage to be applied to the functional MOSFETs based on the applied voltage data.

Claims5

Dependent claims

A semiconductor integrated circuit device comprising a semiconductor integrated circuit including a MOS transistor having a substrate and a source,

wherein a substrate supply voltage and a source supply voltage are separately provided to the MOS transistor,
wherein the substrate is connected to two substrate supply voltage generating units, and the two substrate supply voltage generating units are switched by a control signal;
wherein:
at least one of the substrate voltage supply generating units comprises a monitor element including a monitor MOS transistor, a current source, a comparator, and an amplifier configured to receive an output from the comparator and output the substrate supply voltage applied to said MOS transistor in the semiconductor integrated circuit,
a drain of the monitor MOS transistor of the monitor element is connected to the current source;
the comparator is configured to compare a drain voltage of the monitor MOS transistor with a signal indicative of a leak current of the MOS transistor in the semiconductor integrated circuit;
a substrate voltage of the amplifier is adjusted such that a drain voltage of the MOS transistor in the semiconductor integrated circuit is equal to the substrate supply voltage supplied to the semiconductor integrated circuit;
and
a gate voltage of the monitor MOS transistor of the monitor element is controlled by the control signal.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/706,955Filed 16 Feb 2007 · continuation
Priority: JP P. 2004-0012596 Jan 2004
Published: US 2007/0146049 A128 Jun 2007
Granted: 29 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

H03K 19/0013
Arrangements for reducing power consumption: in field effect transistor circuits
H03K 19/00384
Modifications for compensating variations of temperature, supply voltage or other physical parameters: in field effect transistor circuits
H03K
Pulse technique

Family

Application11/002,703Parent of this continuation · filed 3 Dec 2004
US 2007/0146049 A1Pre-grant publication · published 28 Jun 2007
US 7,196,571 B2Parent of this continuation
US 2005/0146374 A1Published application
US 7,405,611 B2This patent

From the US filing history. Foreign family members aren’t listed.