D flip-flop
AssigneeIntellectual Ventures Fund 27 LLC
InventorsChi Wah Kok, Yee Ching Tam
Life of this patent
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Abstract
A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.
Claims21
A D flip-flop, comprising:
- a master stage comprising a first data input line, a first clock line, a first data output line, and a storage circuit configured to store a signal applied at the first data input line;
- a slave stage comprising a second data input line operatively connected to the first data output line, a second clock line and a second data output line, and further comprising:
- a storage circuit;
- and
- a first switching element configured to electrically connect the input terminal of the storage circuit to the second data input line in response to a state of clock signal present on the second clock line, and
- a clock gating circuitry comprising
- an XNOR gate having two inputs connected to the first data input line and second data output line, respectively, and an output;
- a gating switching transistor having a gate connected to the output of the XNOR gate;
- and
- a gating inverter having an input adapted to connect to an external source of clock pulses, and output connected to the first clock line, and an enable input connected to the switching transistor as a load.
A D flip-flop, comprising:
- a master stage comprising a first data input line, a first clock line, a first data output line, and a first storage circuit configured to store a signal applied at the first data input line;
- a slave stage comprising a second data input line operatively coupled to the first data output line and a second data output line;
- and
- a clock gating circuitry comprising
- an XNOR gate having two inputs coupled to the first data input line and second data output line, respectively, and an output;
- a gating switching transistor having a gate coupled to the output of the XNOR gate;
- and
- a gating inverter having an input adapted to couple to an external source of clock pulses, and an output coupled to the first clock line, and an enable input coupled to the switching transistor as a load.
Dependencies are inferred from the claim text.