Variable delay clock circuit and method thereof
AssigneeRealtek Semiconductor Corp.
InventorsChia-Liang Lin, Gerchih Chou
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Abstract
An apparatus for generating an output clock is disclosed. The apparatus comprises: N variable offset clock circuits for receiving N input clocks and for generating N intermediate clocks having N phase offsets controlled by N intermediate signals, respectively, where N>1; a clock multiplexer for selecting one of the N intermediate clocks as the output clock according to a finite-state signal having N possible states; and a finite-state-machine for receiving a control signal and the N intermediate clocks and for generating the finite-state signal and the N intermediate signals.
Claims22
A method for generating an output clock, the method comprising:
- receiving a control signal and N input clocks, where N>1;
- delaying the N input clocks according to N intermediate signals to generate N intermediate clocks, respectively;
- selecting one of the N intermediate clocks as the output clock according to a finite-state signal;
- and
- generating the finite-state signal and the N intermediate signals in response to the control signal and the N intermediate clocks.
An apparatus for generating an output clock, the apparatus comprising:
- N variable offset clock circuits for receiving N input clocks and for delaying the N input clocks according to N intermediate signals to generate N intermediate clocks, respectively, where N>1;
- a clock multiplexer for selecting one of the N intermediate clocks as the output clock according to a finite-state signal;
- and
- a finite-state-machine (FSM) for receiving a control signal and the N intermediate clocks and for generating the finite-state signal and the N intermediate signals.
Dependencies are inferred from the claim text.