Reset control circuit and reset control method
AssigneeFujitsu Limited
InventorTeruhiko Saitou
Life of this patent
Estimating the term…
Abstract
To present a reset control circuit and a reset control method used in a system including clock synchronous circuit, capable of resetting appropriately, especially in case of abnormality, when the clock signal is stopped or its period is longer as compared with the reset response required for detection of abnormal state. A reset control circuit 200 for output control of reset signal RS depending on reset request signal RR comprises a clock transforming unit 210 for transforming and issuing a clock signal CK, while generating a clock output signal RC at delay of clock output waiting period DC depending on the reset request signal RR, and a reset signal generator 220 for generating a reset signal RS at delay of reset output waiting period D depending on the clock output signal RC.
Claims4
A reset control circuit for output control of a reset signal depending on a reset request signal comprising:
- a reset request delay unit for generating a reset request delay signal which delays the reset request signal for a reset output waiting period, wherein an output signal of the reset request delay unit changes to a polarity the same as a polarity that an input signal of the reset request delay unit has changed to prior to the output signal;
- a reset request hold unit for generating a reset request hold signal which is the reset request signal held synchronously with a clock signal;
- and
- a logical sum operation unit for issuing the logical sum of the reset request delay signal and the reset request hold signal as the reset signal.
A reset control method for output control of a reset signal depending on a reset request signal comprising:
- generating a reset request delay signal which delays the reset request signal by reset output waiting period wherein the reset request delay signal changes to a polarity the same as a polarity that the reset request delay signal has changed to prior to the reset request delay signal;
- and
- generating a reset request hold signal which is the reset request signal held synchronously with a clock signal,
- wherein the reset signal is generated based on a change of either the reset request delay signal or the reset request hold signal, whichever changes earlier.
Dependencies are inferred from the claim text.