Advanced repeater with duty cycle adjustment
AssigneeTransmeta Corporation
InventorScott Pitkethly
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Abstract
An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.
Claims20
A circuit for assisting transitions of a signal on a wire, said circuit comprising:
- an output stage for driving an output signal line responsive to an input signal;
- a plurality of active devices for selectably adjusting a duty cycle of said signal on said wire, wherein a drive level of said output stage remains constant responsive to said adjusting;
- and
- circuitry for producing a delayed version of said signal, characterized by a delay that is greater than a transition time of said output stage less a delay of said plurality of active devices.
A method of assisting transitions of an input signal, said method comprising:
- receiving a transition of said input signal at a circuit input;
- receiving a plurality of control signals to selectively adjust the duty cycle of an output signal generally corresponding to said input signal;
- selectively adjusting said duty cycle;
- driving an output level corresponding to said transition;
- and
- ceasing said driving prior to an arrival at said circuit input of a subsequent transition of said input signal.
A circuit for assisting signal transitions on a wire, said circuit comprising:
- a first transistor for driving a rising edge transition on an output signal line;
- a second transistor for driving a falling edge transition on said output signal line;
- an OR gate having first and second inputs for controlling said first transistor;
- said OR gate further comprising a plurality of pull up transistors for selectably adjusting timing of said rising edge transition, wherein a drive level of said output signal line remains constant responsive to adjustments to said timing of said rising edge transition;
- an AND gate having first and second inputs for controlling said second transistor;
- and
- said AND gate further comprising a plurality of pull down transistors for selectably adjusting timing of said falling edge transition, wherein a drive level of said output signal line remains constant responsive to adjustments to said timing of said falling edge transition.
Dependencies are inferred from the claim text.