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US 7,405,593 B2Granted
Systems and methods for transmitting signals across integrated circuit chips
AssigneeFujitsu Limited
InventorsNestor Tzartzanis, William W. Walker
Life of this patent
Estimating the term…
Abstract
Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.
Claims25
A signal-transmission system comprising:
- a first interconnect wire having a first end and a second end;
- a second interconnect wire having a first end and a second end;
- a first transmission circuit having a data input to receive a data signal to be transmitted, an enable port to receive a transmission-control signal, a first output coupled to the first end of the first interconnect wire, and a second output coupled to the first end of the second interconnect wire, the data signal capable of having a first data value and a second data value, the transmission-control signal capable of having a transmission enable state and a transmission disable state;
- wherein the first transmission circuit comprises:
- a first transistor coupled between a first source of potential and the first end of the first interconnect wire, the first transistor being conductive when the transmission-control signal is in its disable state and non-conductive when the transmission-control signal is in its enable state;
- a second transistor coupled between the first source of potential and the first end of the second interconnect wire, the second transistor being conductive when the transmission-control signal is in its disable state and non-conductive when the transmission-control signal is in its enable state;
- a second potential;
- a first transistor stack coupled between the first and second potentials and to the first end of the first interconnect wire, the first transistor stack forming a conductive path between the first potential and the first end of the first interconnect wire when the transmission-control signal is in its enable state and the first data value is present at the data input, and further forming a conductive path between the second potential and the first end of the first interconnect wire when the transmission-control signal is in its enable state and the second data value is present at the data input;
- and
- a second transistor stack coupled between the first and second potentials and to the first end of the second interconnect wire, the second transistor stack forming a conductive path between the second potential and the first end of the second interconnect wire when the transmission-control signal is in its enable state and the first data value is present at the data input, and further forming a conductive path between the first potential and the first end of the second interconnect wire when the transmission-control signal is in its enable state and the second data value is present at the data input;
- in response to receiving the transmission enable state at its enable port and the first data value at its data input, the first transmission circuit coupling a first current having a first value at the first end of the first interconnect wire and coupling a second current having a second value at the first end of the second interconnect wire, the first and second currents having different values;
- in response to receiving the transmission enable state at its enable port and the second data value at its data input, the first transmission circuit coupling a third current having a third value at the first end of the first interconnect wire and coupling a fourth current having a fourth value at the first end of the second interconnect wire, the third and fourth currents having different values, the first and third currents having different values, and the second and fourth currents having different values;
- a reception circuit comprising a current-mode sense amplifier having a first input coupled to the second end of the first interconnect wire, a second input coupled to the second end of the second interconnect wire, and a data output to provide a signal representation of a binary value received at its inputs.
10 more elements
A method of transmitting data across an integrated-circuit chip with a first interconnect wire and a second interconnect wire, each interconnect wire having a first end in a first area of the integrated-circuit chip, a second end in a second area of the integrated-circuit chip, and a first tap point that lies between the first and second ends in a third area of the integrated-circuit chip, the method comprising:
- coupling at least one current at one of the first ends of the interconnect wires during a first period of time to generate a current difference in the interconnect wires that propagates from the first ends of the interconnect wires to the second ends of the interconnect wires, the current difference having a first sign to represent a first value of data transmitted and a second sign to represent a second value of data transmitted;
- sensing the sign of the current difference at the second ends of the interconnect wires;
- discharging the currents in the first and second interconnect wires in a second period of time that follows after the first period of time;
- coupling at least one current at one of the first tap points of the interconnect wires during a third period of time to generate a current difference in the interconnect wires that propagates from the first tap points of the interconnect wires to the second ends of the interconnect wires, the third period of time occurring after the second period of time, the current difference having a first sign to represent a first value of data transmitted and a second sign to represent a second value of data transmitted;
- sensing the sign of the current difference at the second ends of the interconnect wires;
- and
- discharging the currents in the first and second interconnect wires in a fourth period of time that follows after the third period of time.
4 more elements
Dependencies are inferred from the claim text.