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US 7,405,586 B2Granted
Ultra low pin count interface for die testing
AssigneeIntel Corporation
InventorsSunil Gupta, Reed Linde, Rich Fackenthal
Life of this patent
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Abstract
An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.
Claims24
An apparatus comprising:
- an input/output (I/O) block to communicate with an external tester to receive test data and to send test result using first and second communication modes;
- a logic block coupled to the I/O block to parse the test data;
- a memory coupled to the logic block to store microcode from the parsed test data, the microcode containing a test program to test a circuit;
- and
- a controller coupled to the memory and the logic block to execute the test program.
2 more elements
A method comprising:
- communicating with an external tester to receive test data and to send test result using first and second communication modes;
- parsing the test data to extract microcode, the microcode containing a test program to test a circuit;
- loading the microcode to a memory;
- executing the test program;
- and
- providing the test result.
3 more elements
A system comprising:
- a tester;
- and
- a device under test (DUT) group coupled to the tester and having a plurality of dice, each of the dice having an ultra low pin count (ULPC) interface including a data signal and a dual-function signal, each of the dice comprising:
- an input/output (I/O) block to communicate with the tester to receive test data and to send test result on the data signal using first and second communication modes,
- a logic block coupled to the I/O block to parse the test data,
- a memory coupled to the logic block to store microcode from the parsed test data, the microcode containing a test program to test a circuit, and
- a controller coupled to the memory and the logic block to execute the test program.
4 more elements
Dependencies are inferred from the claim text.