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US 7,405,585 B2Granted
Versatile semiconductor test structure array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYih-Yuh Doong
Life of this patent
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Abstract
This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUT) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.
Claims20
A semiconductor test structure array comprising:
- a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array, each device under test including a plurality of pins for receiving test signals;
- and
- an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,
- wherein the access-control circuitry comprises at least two identical controlled transmission gates (CTGs), each CTG being turned on simultaneously to pass the test signals to a given device under test and a plurality of the access-control circuitries are isomorphic.
1 more element
A semiconductor test structure array comprising:
- a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array, each device under test including a plurality of pins for receiving test signals;
- and
- an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,
- wherein the access-control circuitries are isomorphic and each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), and each CTG being turned on simultaneously to pass the test signals to a given device under test, and
- wherein at least one of the CTGs further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.
2 more elements
A semiconductor test structure array comprising:
- a row decoder;
- a column decoder;
- a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array, each device under test including a plurality of pins for receiving test signals;
- and
- an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,
- wherein the access-control circuitries are isomorphic and each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), each CTG being turned on simultaneously to pass the test signals to a given device under test, and
- wherein the CTG further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.
4 more elements
Dependencies are inferred from the claim text.