Electrical connector for semiconductor device test fixture and test assembly
AssigneeQualiTau, Inc.
InventorPeter P. Cuevas
Life of this patent
Estimating the term…
Abstract
An interconnect assembly is for use in connection with a semiconductor device under test (DUT) having a plurality of leads to electronic test equipment. The interconnect assembly includes a cable including a plurality of wires with at least one wire for sensing a signal from a DUT, at least one wire for a forcing signal to the DUTY and at least one wire for a guarding signal driven by the same electrical potential as the forcing signal. A male connector includes the plurality of wires, an outer metal coating surrounding the plurality of wires, and an insulating coating around the outer metal coating. A receptacle connector is for receiving the male connector and plurality of wires with corresponding contacts.
Claims10
A semiconductor device test apparatus to perform a high voltage test of a device under test (DUT), comprising:
- a plurality of source measurement units (SMUs);
- a plurality of SMU connectors, each SMU connector electrically connected to a corresponding separate one of the plurality of SMUs;
- a tester housing partially enclosing the plurality of SMUs and the plurality of SMU connectors;
- and
- a test fixture, the test fixture configured to be connected to the tester housing such that, in a closed state, the test fixture and the tester housing completely enclose the plurality of SMUs and the plurality of SMU connectors, wherein the test fixture includes
- a socket configured to receive pins of the DUT,
- a plurality of test fixture connectors, each test fixture connector corresponding to a separate pin of the DUT and configured to, via the socket and when connected by a cable to a corresponding separate one of the plurality of SMU connectors, provide a forcing signal from that test fixture connector to that separate pin of the DUT, receive a sensing signal from that separate pin of the DUT at that test fixture connector, and maintain a guard signal at that separate pin of the DUT at a same electrical potential as the forcing signal.
A semiconductor device test apparatus to perform a high voltage test of a device under test (DUT), comprising:
- a plurality of source measurement units (SMUs);
- a plurality of cables, each cable electrically connected to a separate one of the plurality of SMUs;
- a tester housing partially enclosing the plurality of SMUs;
- and
- a test fixture, the test fixture configured to be connected to the tester housing such that, in a closed state, the test fixture and the tester housing completely enclose the plurality of SMUs, wherein the test fixture includes
- a socket configured to receive pins of the DUT,
- a plurality of test fixture connectors, each test fixture connector corresponding to a separate pin of the DUT and configured to, via the socket and when connected by the cable corresponding to a separate one of the plurality of SMUs, provide a forcing signal from that test fixture connector to that separate pin of the DUT, receive a sensing signal from that separate pin of the DUT at that test fixture connector, and maintain a guard signal at that separate pin of the DUT at a same electrical potential as the forcing signal.
Dependencies are inferred from the claim text.