Asymmetric field transistors (FETs)

A semiconductor structure, comprising:

• a semiconductor channel region doped with a first doping polarity;
• a semiconductor source block doped with a second doping polarity and in direct physical contact with the semiconductor channel region;
• a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material, and wherein the semiconductor source block physically isolates the source contact region from the semiconductor channel region, and
• a drain contact region in direct physical contact with the semiconductor channel region, wherein the semiconductor channel region is disposed between the semiconductor source block and the drain contact region, and wherein the drain contact region comprises a second electrically conducting material;
• a gate dielectric region in direct physical contact with the semiconductor channel region, wherein the gate dielectric region and the semiconductor channel region have a first common interfacing surface;
• and
• a gate electrode region in direct physical contact with the gate dielectric region and electrically insulated from the semiconductor channel region by the gate dielectric region,
• wherein the semiconductor channel region and the semiconductor source block are formed on a semiconductor substrate having a top surface essentially perpendicular to the first common interfacing surface of the gate dielectric region and the semiconductor channel region.