Electronic apparatus with deposited dielectric layers
AssigneeMicron Technology, Inc.
InventorsKie Y. Ahn, Leonard Forbes
Life of this patent
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Abstract
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate surface by atomic layer deposition and depositing a hafnium oxide layer on the hafnium metal layer by atomic layer deposition form a hafnium oxide dielectric layer substantially free of silicon oxide. Dielectric layers containing atomic layer deposited hafnium oxide are thermodynamically stable such that the hafnium oxide will have minimal reactions with a silicon substrate or other structures during processing.
Claims28
An electronic device comprising:
- a silicon substrate;
- a dielectric layer disposed on the silicon substrate;
- the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer in contact with the silicon substrate essentially without a SiOx layer contacting the silicon substrate.
A capacitor, comprising:
- a first conductive layer on a silicon substrate;
- a dielectric layer disposed on the first conductive layer, the dielectric layer disposed on the silicon substrate, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the first conductive layer essentially without a SiOx layer contacting the first conductive layer;
- and
- a second conductive layer disposed on the dielectric layer.
A transistor comprising:
- a silicon body region between a source region and a drain region on a silicon substrate;
- a dielectric layer disposed on the silicon body region between the source region and the drain region, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the silicon body region essentially without a SiOx layer contacting the silicon body region;
- and
- a gate coupled to the dielectric layer.
A memory comprising:
- a number of access transistors, at least one access transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a silicon body region between a source region and a drain region on a silicon substrate, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the silicon body region essentially without a SiOx layer contacting the body region;
- a number of word lines coupled to the number of access transistors;
- and
- a number of bit lines coupled to the number of access transistors.
An electronic system comprising:
- a processor;
- a system bus;
- and
- a memory coupled to the processor by the system bus, the memory including:
- a number of access transistors, at least one access transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a silicon body region between a source region and a drain region on a silicon substrate, the dielectric layer having a dielectric film structured as one or more monolayers of a metal oxide, the dielectric film having a surface with a roughness less than or equal to a micro-roughness due to partial monolayer formation of the dielectric film, the dielectric layer having an interfacial layer, the interfacial layer contacting the silicon body region essentially without a SiOx layer contacting the silicon body region;
- a number of word lines coupled to the number of access transistors;
- and
- a number of bit lines coupled to the number of access transistors.
Dependencies are inferred from the claim text.