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US 7,405,450 B2Granted
Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon
AssigneeSamsung Electronics Co., Ltd.
InventorsGyu-Ho Lyu, Soon-moon Jung, Sung-bong Kim, Hoon Lim, Won-Seok Cho
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Abstract
Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is on a sidewall of the gate line. A conductive line pattern is on the gate line. The conductive line pattern is parallel with the gate line and is electrically connected to the gate electrode.
Claims28
A semiconductor device comprising:
- a semiconductor substrate;
- a gate line including a gate insulation pattern, a gate electrode that comprises a doped polysilicon layer and a metal silicide layer which are sequentially stacked on the semiconductor substrate;
- a spacer formed on a sidewall of the gate line;
- a conductive line pattern disposed on the gate line;
- and
- an interlayer dielectric on the semiconductor substrate having a top surface that is coplanar with a top surface of the gate line;
- wherein the conductive line pattern is parallel to the gate line and electrically connected to the gate electrode.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a first gate line and a second gate line on the semiconductor substrate and spaced apart from each other, the first gate line including a first gate electrode stacked on a first gate insulation pattern, and the second gate line including a second gate electrode stacked on a second gate insulation pattern;
- a conductive line pattern on the first and second gate lines, wherein the conductive line pattern has a first portion parallel to the first gate line and a second portion parallel to the second gate line, and wherein the conductive line pattern electrically connects the first and second gate electrodes with each other;
- and
- an interlayer dielectric on the semiconductor substrate that is planarized to the height of the first and second gate lines, wherein the conductive line pattern is also disposed on the interlayer dielectric between the first and second gate lines;
- wherein the first and second gate lines each comprise a metal silicide layer on a doped polysilicon layer.
3 more elements
A semiconductor device, comprising:
- a gate electrode on a semiconductor substrate, the gate electrode including a polysilicon layer and a metal silicide layer which are sequentially stacked;
- and
- a conductive line pattern on the gate electrode, the conductive line pattern extending in a first direction and being in contact with the gate electrode along the first direction,
- wherein the first direction is substantially parallel to a longitudinal direction of the gate electrode.
1 more element
A semiconductor device comprising:
- a semiconductor substrate;
- a first gate line and a second gate line on the semiconductor substrate and spaced apart from each other, the first gate line including a first gate electrode stacked on a first gate insulation pattern, and the second gate line including a second gate electrode stacked on a second gate insulation pattern;
- a conductive line pattern on the first and second gate lines, wherein the conductive line pattern has a first portion parallel to the first gate line and a second portion parallel to the second gate line, and wherein the conductive line pattern electrically connects the first and second gate electrodes with each other;
- wherein the first and second gate lines each comprise a metal silicide layer on a doped polysilicon layer;
- wherein the conductive line pattern is a metal line pattern that is on the metal silicide layer.
2 more elements
Dependencies are inferred from the claim text.