Nonvolatile semiconductor memory

A nonvolatile semiconductor memory on a semiconductor chip, comprising:

• a cell array region configured with device isolating regions in a semiconductor substrate arranged in parallel to device activating regions in a memory cell transistor comprising a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a floating gate electrode adjacent to the first control gate electrode;
• a high voltage circuit region including a high voltage transistor made of a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region;
• a low voltage circuit region including a low voltage transistor made of a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and electrically coupled with the third metallic salicide film;
• a fourth metallic salicide film arranged on the semiconductor chip;
• an interconnect region electrically coupled with the fourth metallic salicide film;
• and
• a resistive element region electrically insulated from the first through fourth metallic salicide fllms,
• wherein the resistive element region is formed on the device isolating regions in the semiconductor substrate.

A nonvolatile semiconductor memory on a semiconductor chip, comprising:

• a cell array region configured with device isolating regions in a semiconductor substrate arranged in parallel to device activating regions in a memory cell transistor comprising a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a floating gate electrode adjacent to the first control gate electrode;
• a high voltage circuit region including a high voltage transistor made of a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region;
• a low voltage circuit region including a low voltage transistor made of a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and electrically coupled with the third metallic salicide film, wherein the second metallic salicide film is electrically coupled with only a part of the first source region and the first drain region;
• a fourth metallic salicide film arranged on the semiconductor chip;
• an interconnect region electrically coupled with the fourth metallic salicide film;
• and
• a resistive element region electrically insulated from the first through fourth metallic salicide fllms,
• wherein the resistive region is formed on the device isolating regions in the semiconductor substrate.