Memory cell structure and semiconductor memory device

The memory cell structure, comprising:

• a first memory capacitor arranged in a local area and comprised of a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode;
• a second memory capacitor arranged in the local area, spaced apart from the first memory capacitor, and comprised of a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode;
• a local interconnection layer that is electrically conductive and impermeable to hydrogen, extends within the local area, and is comprised of a first contact portion that is in contact with the first upper electrode and spaced apart from the first dielectric oxide film by the first upper electrode, a second contact portion that is in contact with the second upper electrode and spaced apart from the second dielectric oxide film by the second upper electrode, and a non-contact portion that connects the first contact portion to the second contact portion and is spaced apart from the first and second memory capacitors;
• a hydrogen barrier layer that is electrically insulating and impermeable to hydrogen, and is interposed between each of the first dielectric oxide film, the second dielectric oxide film, and the non-contact portion to separate the first dielectric oxide film and the first upper electrode from the non-contact portion, and to separate the second dielectric oxide film and the second upper electrode from the non-contact portion;
• and
• an insulating film that is electrically insulating and permeable to hydrogen, and interposed between the non-contact portion and the hydrogen barrier layer.

A semiconductor memory device, comprising:

• a word line;
• a non-inverted bit line;
• a inverted bit line;
• a global interconnection layer;
• a first memory capacitor comprised of a first accumulation electrode, a first counter electrode, and a first dielectric oxide film interposed between the first accumulation electrode and the first counter electrode;
• a second memory capacitor comprised of a second accumulation electrode, a second counter electrode, and a second dielectric oxide film interposed between the second accumulation electrode and the second counter electrode;
• a local interconnection layer that is electrically conductive and impermeable to hydrogen, and comprised of a first contact portion that is in contact with the first counter electrode and spaced apart from the first dielectric oxide film by the first counter electrode, a second contact portion that is in contact with the second counter electrode and spaced apart from the second dielectric oxide film by the second counter electrode, a non-contact portion that connects the first contact portion to the second contact portion and is spaced apart from the first and second memory capacitors;
• a hydrogen barrier layer that is electrically insulating and impermeable to hydrogen, and covers at least the first and second contact portions of the local interconnection layer;
• a first switching transistor comprised of a first gate electrode that is electrically connected to the word line, and providing an electrical connection between the non-inverted bit line and the first accumulation electrode;
• a second switching transistor comprised of a second gate electrode that is electrically connected to the word line, and providing an electrical connection between the first inverted bit line and the second accumulation electrode;
• and
• a third switching transistor comprised of a third gate electrode that is electrically connected to the word line, and providing an electrical connection between the local interconnection layer and the global interconnection layer.

A semiconductor memory device, comprising:

• a word line;
• a non-inverted bit line;
• an inverted bit line;
• a global interconnection layer;
• a first memory capacitor comprised of a first accumulation electrode, a first counter electrode, and a first dielectric oxide film interposed between the first accumulation electrode and the first counter electrode;
• a second memory capacitor comprised of a second accumulation electrode, a second counter electrode, and a second dielectric oxide film interposed between the second accumulation electrode and the second counter electrode;
• a local interconnection layer that is electrically conductive and impermeable to hydrogen, and comprised a first contact portion that is in contact with the first counter electrode and spaced apart from the first dielectric oxide film by the first counter electrode, a second contact portion that is in contact with the second counter electrode and spaced apart from the second dielectric oxide film by the second counter electrode, and a non-contact portion that connects the first contact portion to the second contact portion and is spaced apart from the first and second memory capacitors;
• a hydrogen barrier layer that is electrically insulating and impermeable to hydrogen, and surrounds the first and second contact portions of the local interconnection layer and covers the side and upper surfaces of the first and second memory capacitors;
• an insulating film that is electrically insulating and permeable to hydrogen, and interposed between the non-contact portion of the local interconnection layer and the second hydrogen barrier layer;
• a first switching transistor comprised of a first gate electrode electrically connected to the word line, and providing an electrical connection between the first non-inverted bit line and the first accumulation electrode of the first memory capacitor;
• a second switching transistor comprised of a second gate electrically connected to the word line, and providing an electrical connection between the inverted bit line and the second accumulation electrode of the second memory capacitor;
• and
• a third switching transistor comprised of a third gate electrode electrically connected to the word line, and providing an electrical connection between the local interconnection layer and the global interconnection layer.

A semiconductor memory device, comprising:

• a word line;
• a plate line;
• a first memory capacitor comprised of a first accumulation electrode, a first counter electrode, and a first dielectric oxide film interposed between the first accumulation electrode and the first counter electrode;
• a second memory capacitor comprised of a second accumulation electrode, a second counter electrode, and a second dielectric oxide film interposed between the second accumulation electrode and the second counter electrode;
• a first local interconnection layer that is electrically conductive and impermeable to hydrogen, and comprised of a first contact portion that is in contact with the first counter electrode and spaced apart from the first dielectric oxide film by the first counter electrode, a second contact portion that is in contact with the second counter electrode and spaced apart from the second dielectric oxide film by the second counter electrode, and a first non-contact portion that connects the first contact portion to the second contact portion of the first local interconnection layer and is spaced apart from the first and second memory capacitors;
• and
• a switching transistor having source and drain electrodes, and having a gate electrode electrically connected to the word line, one electrode from among the source and drain electrodes being connected to the plate line and another electrode from among the source and drain electrodes being connected to the first local interconnection layer, wherein the another electrode from among the source and drain electrodes is disposed between the first memory capacitor and the second memory capacitor.