US 7,405,436 B2 · Stressed field effect transistors on hybrid orientation substrate

Abstract

A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

Claims9

Dependent claims

A method for fabricating a semiconductor structure having improved carrier mobility comprising:

providing a hybrid oriented substrate having first and second planar surfaces comprising a first semiconductor material and a second semiconductor material, respectively, said first and second semiconductor materials comprising different crystallographic orientations, and
forming at least one CMOS device on each of the planar surfaces of different crystallographic orientations wherein each CMOS device has a stressed channel and a stress inducing liner, wherein said stress inducing liner on said first planar surface is a tensile stress inducing material, said stress inducing liner on said second planar surface is a compressively stress inducing material.

Dependencies are inferred from the claim text.

Facts

Application

11/029,797Filed 5 Jan 2005

Published

US 2006/0145264 A16 Jul 2006

Granted

29 Jul 2008

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 62/405
Crystalline structures: orientations of crystalline planes
H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Stressed field effect transistors on hybrid orientation substrate

Life of this patent

Stressed field effect transistors on hybrid orientation substrate

Life of this patent

Abstract

Claims9