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US 7,405,429 B2Granted
Pixel structure
AssigneeAU Optronics Corp. (AUO)
InventorChin-Kuo Ting
Life of this patent
Estimating the term…
Abstract
A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer beside the patterned polysilicon layer forms a source and a drain. A gate insulation layer is formed on the substrate to cover the source, the drain and the patterned polysilicon layer. A gate is formed on the gate insulation layer over the patterned polysilicon layer.
Claims4
A pixel structure, comprising:
- a patterned polysilicon layer disposed on a substrate;
- a source and a drain disposed on the respective sides of the patterned polysilicon layer, wherein the source and the drain are made of metallic material;
- a data line disposed on the substrate and electrically connected to the source;
- a gate insulation layer disposed on the substrate covering the data line, the source, the drain and the patterned polysilicon layer;
- a gate disposed on the gate insulation layer over the patterned polysilicon layer;
- a scan line disposed on the gate insulation layer and electrically connected to the gate;
- a first dielectric layer covering the gate and the scan line;
- and
- a pixel electrode disposed on the first dielectric layer and electrically connected to the drain.
6 more elements
A pixel structure, comprising:
- a patterned polysilicon layer disposed on a substrate;
- a source and a drain disposed over the substrate on the respective sides of the patterned polysilicon layer, wherein the source and the drain are made of metallic material;
- a data line disposed over the substrate and electrically connected to the source;
- a gate insulation layer covering the source, the drain and the patterned polysilicon layer;
- a gate disposed on the gate insulation layer;
- a scan line disposed on the gate insulation layer and electrically connected to the gate;
- a first dielectric layer disposed over the gate and the scan line;
- a first metal contact layer and a second metal contact layer disposed over the first dielectric layer and electrically connected to the source and the drain respectively;
- a second dielectric layer disposed on the first dielectric layer to cover the first metal contact layer and the second metal contact layer;
- and
- a pixel electrode disposed on the second dielectric layer and electrically connected to the second metal contact layer.
8 more elements
Dependencies are inferred from the claim text.