US 7,405,131 B2 · Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor

Abstract

The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.

Claims26

Dependent claims

A method for forming an integrated circuit comprising:

providing a substrate prepared with isolation regions and a gate of a transistor on a device region within the isolation regions;
recessing the substrate in regions adjacent to the gate and isolation regions to create recesses;
forming stressors in the recesses, the stressors induce a stress in a channel region beneath the gate, wherein a stressor comprises a top surface having a horizontal portion and a sloping portion relative to a top surface of the substrate, with the horizontal portion located adjacent to the gate and the sloping portion located adjacent to the isolation region;
and
forming dielectric stressor spacers on the sloping portions of the stressors, wherein the dielectric stressor spacers reduce silicide strapping of the source and drain to body.

2 more elements

Dependencies are inferred from the claim text.

Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor

Life of this patent

Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor

Life of this patent

Abstract

Claims26