Method for producing a vertical field effect transistor
AssigneeInfineon Technologies AG
InventorHelmut Tews
Life of this patent
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Abstract
A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.
Claims10
A method for producing a vertical field effect transistor comprising the following steps:
- forming of at least one structure on a substrate which serves for forming the channel region of a field effect transistor;
- applying an electrically insulating spacer layer near to the substrate after the formation of the structure;
- applying an electrically conductive or semiconducting control electrode layer which serves for forming the control electrode of the field effect transistor;
- planarization of the control electrode layer;
- whole-area etching-back of the planarized control electrode layer;
- and prior to applying the control layer electrode, the steps of:
- planarizing the spacer layer near to the substrate;
- and whole-area etching-back of the spacer layer near to the substrate.
A method for producing a vertical field effect transistor comprising the following steps:
- forming of at least one structure on a substrate which serves for forming the channel region of a field effect transistor;
- applying an electrically insulating spacer layer near to the substrate after the formation of the structure;
- applying an electrically conductive or semiconducting control electrode layer which serves for forming the control electrode of the field effect transistor;
- planarization of the control electrode layer;
- whole-area etching-back of the planarized control electrode layer;
- and
- applying an electrically insulating spacer layer remote from the substrate after the etching-back of the control electrode layer;
- planarizing the spacer layer remote from the substrate;
- and
- whole-area etching-back of the spacer layer remote from the substrate.
A method for producing a vertical field effect transistor comprising the following steps:
- forming of at least one structure on a substrate which serves for forming the channel region of a field effect transistor;
- applying an electrically insulating spacer layer near to the substrate after the formation of the structure;
- applying an electrically conductive or semiconducting control electrode layer which serves for forming the control electrode of the field effect transistor;
- planarization of the control electrode layer;
- whole-area etching-back of the planarized control electrode layer;
- and
- forming an electrically insulating layer on a part of the structure near the substrate after the etching-back of the spacer layer and prior to the application of the control electrode layer.
A method for producing a vertical field effect transistor comprising the following steps:
- forming of at least one structure on a substrate which serves for forming the channel region of a field effect transistor;
- applying an electrically insulating spacer layer near to the substrate after the formation of the structure;
- applying an electrically conductive or semiconducting control electrode layer which serves for forming the control electrode of the field effect transistor;
- planarization of the control electrode layer;
- whole-area etching-back of the planarized control electrode layer;
- and
- applying a charge storage layer near to the substrate after the application of the spacer layer and prior to the application of the control electrode layer;
- patterning the charge storage layer prior to the application of the control electrode layer.
Dependencies are inferred from the claim text.