Methods for forming co-planar wafer-scale chip packages

A method for forming a multi-chip wafer level package, comprising the steps of:

• forming a plurality of different-type chips on a corresponding chip substrate;
• detaching said plurality of chips from said corresponding chip substrate;
• forming a plurality of pockets on a carrier substrate such that each of the plurality of pockets hold a predetermined-type chip;
• selecting chip from the plurality of different-type chips that correspond to the predetermined-type chip for each of the plurality of pockets;
• and
• mounting the selected chips into their corresponding pocket such that a top surface of the selected chip is substantially co-planar with a top surface of the carrier substrate,
• wherein forming pockets in the carrier substrate comprises:
• forming oxide regions on a surface of the carrier substrate;
• partially bonding a semiconductor wafer to the surface of the carrier substrate;
• that the semiconductor wafer is bonded only to the oxide regions on the surface of the carrier substrate, while the semiconductor wafer in not bonded to non-oxide regions on the surface of the carrier substrate;
• and
• partially dicing the semiconductor wafer to remove portions of the wafer that are not bonded to the surface of the carrier substrate to form the pockets.

A method for forming a multi-chip wafer level package, comprising the steps of:

• forming shallow trench isolation (STI) regions on a surface of a chip substrate;
• partially bonding a wafer to the STI regions on the surface of the chip substrate such that voids are formed adjacent to the STI regions in non-bonded regions between the wafer and the chip substrate, wherein areas in the wafer above the STI regions define inter-chip areas and areas in the wafer above the void define chip areas;
• thinning the wafer;
• forming devices in the chip areas of the thinned wafer;
• forming BEOL interconnects on the thinned wafer;
• and
• forming finishing devices and interconnects in the chip areas to complete the formation of a plurality of chips.

A method for forming a multi-chip wafer level package, comprising the steps of:

• forming shallow trench isolation (STI) regions on a surface of a carrier substrate;
• partially bonding a wafer to the STI regions on the surface of the carrier substrate such that voids are formed adjacent to the STI regions in non-bonded regions between the wafer and the carrier substrate, wherein areas in the wafer above the STI regions define inter-chip areas and areas in the wafer above the voids define chip areas
• thinning the wafer;
• forming BEOL interconnects on the thinned wafer;
• coating a top surface of the thinned wafer with a passivation layer;
• and
• dicing a channel in the chip areas of the thinned wafer such that a predetermined portions of said thinned wafer are detached, thereby forming pockets within the thinned wafer.