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US 7,405,101 B2Granted
CMOS imager with selectively silicided gate
AssigneeMicron Technology, Inc.
InventorHoward E. Rhodes
Life of this patent
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Abstract
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
Claims5
A method of forming an imager, comprising:
- forming an array of pixel cells comprising:
- forming a plurality of gates;
- forming a silicide on at least a portion of said plurality of gates;
- and
- removing said silicide from at least a portion of at least one of said plurality of gates,
- wherein forming said plurality of gates includes forming a photogate and said removing act comprises removing said silicide from part of said photogate.
3 more elements
A method of forming a pixel cell, comprising:
- forming a polysilicon layer over a substrate comprising a doped region;
- forming a photogate insulator over said doped region;
- forming a metal layer over said photogate insulator and said polysilicon;
- forming a silicide from said metal layer over said polysilicon layer;
- removing a part of said metal layer over said photogate insulator, wherein said
- removing act comprises retaining said sillicide over said polysilicon layer;
- forming a first gate over said doped region from said polysilicon layer;
- and forming a second gate from said silicide and said poly silicon layer.
5 more elements
Dependencies are inferred from the claim text.